Datasheet

LTC3773
4
3773fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3773 is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. T
J
is calculated from the ambient
temperature T
A
and power dissipation P
D
according to the following
formula.
LTC3773EG: T
J
= T
A
+ (P
D
x 95°C/W)
LTC3773EUHF: T
J
= T
A
+ (P
D
x 34°C/W)
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specifi ed.
Note 4: The IC is tested in a feedback loop that adjusts V
FB
to achieve a
specifi ed error amplifi er output voltage (V
ITH
).
Note 5: Guaranteed by design, not subject to test.
Note 6: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 7: R
DS(ON)
limit is guaranteed by design and/or correlation to static
test.
Note 8: The minimum on-time condition corresponds to an inductor
peak-to-peak ripple current of ≥40% of I
MAX
(see minimum on-time
considerations in the Applications Information section).
(Note 3) The ● denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at T
A
= 25°C. V
CC
= V
DR
= V
BOOST
= V
SDB
= 5V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Good Output Indication
V
PGL
PGOOD Voltage Output Low I
PGOOD
= 2mA 0.1 0.3 V
I
PGOOD
PGOOD Output Leakage V
PGOOD
= 5V 1 μA
V
PGTHNEG
V
PGTHPOS
PGOOD Trip Thresholds
V
FB
Ramping Negative
V
FB
Ramping Positive
V
FB
with Respect to 0.6V Reference
PGOOD Goes Low After V
PGDLY
Delay –7
7
–10
10
–13
13
%
%
V
PGDLY
PGOOD Delay 100 150 μs
Oscillator and Phase-Locked Loop
f
NOM
Nominal Frequency V
PLLFLTR
Open 360 400 440 kHz
f
LOW
Low Frequency V
PLLFLTR
= 0V 190 220 250 kHz
f
HIGH
High Frequency V
PLLFLTR
= 5V 510 560 630 kHz
f
PLLLOW
PLLIN Minimum Input Frequency 160 200 kHz
f
PLLHIGH
PLLIN Maximum Input Frequency 540 700 kHz
V
LO
V
FLOAT
V
HI
PLLIN/FC, PHASEMD, PLLFLTR
Logic Input
Low Level Input Voltage
Floating Voltage
High Level Input Voltage
1.0
1.6
3.0
V
V
V
V
PLLIN
PLLIN Synchronization Input Threshold 1 V
I
PLLFLTR
Phase Detector Output Current
Sinking Capability
Sourcing Capability
V
PLLFLTR
= 1.5V
f
PLLIN
< f
OSC
f
PLLIN
> f
OSC
25
–25
μA
μA
P
RELPHS
Controller 2 - Controller 1 Phase
Controller 3 - Controller 1 Phase
PHASEMD Floats or V
PHASEMD
= 0V 120
240
Deg
Deg
Controller 2 - Controller 1 Phase
Controller 3 - Controller 1 Phase
V
PHASEMD
= 5V 90
270
Deg
Deg
CLKOUT Controller 1 TG to CLKOUT Phase PHASEMD Floats
V
PHASEMD
= 0V
V
PHASEMD
= 5V
0
60
180
Deg
Deg
Deg