Datasheet

LTC3773
24
3773fb
DIGITAL
PHASE/
FREQUENCY
DETECTOR
V
CC
V
CC
R
PLLFL2
C
LP
3773 F07
PLLFLTR
R
PLLFL1
PHASE
DETECTOR/
OSCILLATOR
PLLIN/FC
BG1
CLKOUT
OSCILLATOR
Figure 7. Fixed Frequency Adjustment
The LTC3773 can be confi gured to operate at any switch-
ing frequency within the synchronization range. Figure 7
shows a simple circuit to achieve this. The resistive divider
at the PLLFLTR pin programs the LTC3773 switching
frequency according to the transfer curve of Figure 6b. By
connecting the PLLIN/FC pin to the BG1 or the CLKOUT
(UHF package only) node, the pre-set frequency selection
is disengaged and the PLLFLTR pin potential determines
the switching frequency.
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a signifi cant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If an application can operate close to the minimum on-time
limit, an inductor must be chosen that is low enough in
value to provide suffi cient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30% of I
OUT(MAX)
at V
IN(MAX)
.
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
%Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Checking Transient Response
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to ΔI
LOAD
• ESR, where ESR is the effective
series resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
, generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time, V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I
TH
pin not only allows optimization of
control loop behavior, but also provides a DC coupled and
AC fi ltered closed-loop response test point. The DC step,
rise time and settling at this test point truly refl ects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
t
ON(MIN)
<
V
OUT
V
IN
(f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the IC will begin to skip every
other cycle, resulting in half-frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the IC is generally about
130ns. However, as the peak sense voltage decreases,
the minimum on-time gradually increases. This is of par-
ticular concern in forced continuous applications with low
APPLICATIONS INFORMATION