Datasheet

LTC3773
16
3773fb
mainly depends on the price vs size requirements and any
radiated fi eld/EMI requirements. New designs for high cur-
rent surface mount inductors are available from numerous
manufacturers, including Coiltronics, Vishay, TDK, Pulse,
Panasonic, Vitec, Coilcraft, Toko and Sumida.
Power MOSFET and Schottky Diode Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than 1/3 of the input voltage. In applications where
V
IN
>> V
OUT
, the top MOSFETs’ on-resistance is normally
less important for overall effi ciency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturers have designed special purpose devices that
provide reasonably low on-resistance with signifi cantly
reduced input capacitance for the main switch application
in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by
the driver supply voltage, V
DR
, requiring the use of logic-
level threshold MOSFETs in most applications. Pay close
attention to the BV
DSS
specifi cation for the MOSFETs as
well; many of the logic-level MOSFETs are limited to 30V
or less.
Selection criteria for the power MOSFETs include the on-
resistance R
DS(ON)
, input capacitance, input voltage and
maximum output current. MOSFET input capacitance is
a combination of several components but can be taken
from the typical “gate charge” curve included on most data
sheets as shown in Figure 2. The curve is generated by
forcing a constant input current into the gate of a common
source, current source loaded stage and then plotting the
gate voltage versus time. The initial slope is the effect of the
gate-to-source and the gate-to-drain capacitance. The fl at
portion of the curve is the result of the Miller multiplication
effect of the drain-to-gate capacitance as the drain drops the
voltage across the current source load. The upper sloping
line is due to the drain-to-gate accumulation capacitance
and the gate-to-source capacitance.
The Miller charge (the increase in coulombs on the hori-
zontal axis from A to B while the curve is fl at) is specifi ed
for a given V
DS
drain voltage, but can be adjusted for
different V
DS
voltages by multiplying by the ratio of the
application V
DS
to the curve specifi ed V
DS
values. A way
to estimate the C
MILLER
term is to take the change in gate
charge from points A and B on a manufacturers data sheet
and divide by the stated V
DS
voltage specifi ed. C
MILLER
is the most important selection criterion for determining
the transition loss term in the top MOSFET but is not di-
rectly specifi ed on MOSFET data sheets. C
RSS
and C
OS
are
specifi ed sometimes but defi nitions of these parameters
are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V
OUT
V
IN
Synchronous Switch Duty Cycle =
V
IN
–V
OUT
V
IN
The power dissipation for the main and synchronous
MOSFETs at maximum output current is given by:
P
MAIN
=
V
OUT
V
IN
(I
MAX
2
)(1+ )R
DS(ON)
+
V
IN
2
I
MAX
2
(R
DR
)(C
MILLER
)•
1
V
DR
–V
TH(IL)
+
1
V
TH(IL)








(f)
P
SYNC
=
V
IN
–V
OUT
V
IN
(I
MAX
2
)(1+ )R
DS(ON)
Figure 2. MOSFET Miller Capacitance
APPLICATIONS INFORMATION
MILLER EFFECT
BA
V
DS
V
GS
V
IN
Q
IN
C
MILLER
= (Q
B
– Q
A
)/V
DS
+
+
–
–
+
–
3773 F02
V
GS