Datasheet

LTC3773
10
3773fb
SENSE1
+
(Pin 1/Pin 34): The (+) Input to the Channel 1
Differential Current Comparator. The I
TH1
pin voltage and
controlled offsets between the SENSE1
–
and SENSE1
+
pins in conjunction with R
SENSE
set the channel 1 current
trip threshold.
SENSE1
–
(Pin 2/Pin 35): The (–) Input to the Channel 1
Differential Current Comparator.
SDB/SDB1, SDB2, SDB3 (Pin 3/Pins 36, 37, 38): Shut-
down, Active Low. For G package, SDB1, SDB2 and SDB3
are shorted at the SDB pin. The power up thresholds for
channel 1, 2 and 3 are set at 1.2V, 1.8V and 2.4V respec-
tively. By pulling the SDB1, SDB2 and SDB3 pins below
0.4V, the IC is put into low current shutdown mode (I
VCCQ
<30μA). There is a 0.5μA pull-up current at each SDB pin.
An external capacitor can be added at this pin to provide
power up delay.
TRACK1 (Pin 4/Pin 1): Channel 1 Tracking Input. TRACK1
is used for tracking multiple LTC3773s. See the Startup
Tracking application. To disable this feature, fl oat this pin
or tie it to V
CC
. TRACK1 provides a 1μA pull-up current.
An external capacitor can be added at this pin to provide
soft-start. During startup or output short-circuit condition,
if the potential at TRACK1 is less than 0.54V, current limit
foldback is disabled. When channel 1 is powered down,
this pin will be pulled low.
V
FB1
(Pin 5/Pin 2): Channel 1 Error Amplifi er Feedback
Input. This pin connects the error amplifi er input to an
external resistive divider from V
OUT1
.
I
TH1
(Pin 6/Pin 3): Channel 1 Error Amplifi er Output and
Switching Regulator Compensation Point. The current
comparator’s threshold increases with this control volt-
age.
SGND (Pin 7/Pin 4): Signal Ground. This pin must be
routed separately under the IC to the PGND pin and then
to the main ground plane.
I
TH2
(Pin 8/Pin 5): Channel 2 Error Amplifi er Output and
Switching Regulator Compensation Point. See I
TH1
.
I
TH3
(Pin 9/Pin 6): Channel 3 Error Amplifi er Output and
Switching Regulator Compensation Point. See I
TH1
.
V
FB2
(Pin 10/Pin 7): Channel 2 Error Amplifi er Feedback
Input. See V
FB1
.
V
FB3
(Pin 11/Pin 8): Channel 3 Error Amplifi er Feedback
Input. See V
FB1
.
TRACK2 (Pin 12/Pin 9): Channel 2 Tracking Input. Tie the
TRACK2 pin to a resistive divider connected to the output
of channel 1 for either coincident or ratiometric output
tracking. See the Soft-Start/Tracking application. TRACK2
comes with a 1μA pull-up current. An external capacitor
can be added at this pin to provide soft-start. During
startup or output short-circuit condition, if the potential
at TRACK2 is less than 0.54V, current limit foldback is
disabled. When channel 2 is powered down, this pin will
be pulled low.
TRACK3 (Pin 13/Pin 10): Channel 3 Tracking Input. See
TRACK2.
SENSE2
–
(Pin 14/Pin 11): The (–) Input to the Channel 2
Differential Current Comparator. See SENSE1
–
.
SENSE2
+
(Pin 15/Pin 12): The (+) Input to the Channel 2
Differential Current Comparator. See SENSE1
+
.
SENSE3
–
(Pin 16/Pin 13): The (–) Input to the Channel 3
Differential Current Comparator. See SENSE1
–
.
SENSE3
+
(Pin 17/Pin 14): The (+) Input to the Channel 3
Differential Current Comparator. See SENSE1
+
.
V
CC
(Pin 18/Pin 15): Main Input Supply. All internal circuits
except the output drivers are powered from this pin. V
CC
should be connected to a low noise 5V power supply and
should be bypassed to SGND with at least a 1μF capacitor
in close proximity to the LTC3773.
PLLFLTR (Pin 19/Pin 16): Phase-Locked Loop Lowpass
Filter. The phase-locked loop’s lowpass fi lter is tied to this
pin. Alternatively, when external frequency synchronizing
is not used, this pin can be forced low, left fl oating or tied
high to vary the frequency of the internal oscillator.
PIN FUNCTIONS
(G/UHF)