Datasheet

LTC3766
9
3766fa
For more information www.linear.com/LTC3766
pin FuncTions
(SSOP/QFN)
FGD (Pin 20/Pin 17): Forward Gate Rising Edge Delay. A
resistor to GND sets the delay from PT
+
rising to FG rising
(and SG falling). This delay is used to optimize the dead
time between the turn-off of SG and the turn-on of the
primary-side MOSFET. In standalone mode (100k or 50k
resistor on MODE), this dead time is set adaptively and
the FGD pin can be grounded. See Setting the Gate Driver
Delays in the Applications Information section.
NDRV (Pin 21/Pin 18): Drive Output for the External Pass
Device of the High Voltage Linear Regulator Controller.
Connect to the base (NPN) or gate (MOSFET) of an exter
-
nal N-type device. Tie to V
CC
pin if only using the internal
LDO (V
AUX
pin).
V
IN
(Pin 22/Pin 19): Connect to a higher voltage bias
supply when using the linear regulator controller. The V
IN
pin supplies bias to the internal standby and monitoring
circuits, the linear regulator controller, and the differential
amplifier. Tie to V
AUX
pin if only using the internal LDO.
SW (Pin 23/Pin 20): Connect (Kelvin) to the drain of the
synchronous MOSFET. This input is used for adaptive
shoot-through prevention and leading-edge blanking,
monitoring the high level SW node voltage and SG reverse-
current protection. When SW is high, the voltage on this
pin is internally measured for use in the inductor ripple
cancellation and volt-second limit circuits. When SW is
low and SG is high, this pin sources a small current and
is used for SG reverse overcurrent protection. A resistor
can be placed between the SW pin and the drain of the
synchronous MOSFET to adjust the SG reverse-overcurrent
threshold. The SW pin is internally clamped to 50V.
V
AUX
(Pin 24/Pin 21): Auxiliary Power Input. This is the
power input to an internal LDO that is connected to V
CC
.
Whenever V
AUX
is greater than 4.7V (or 8V for high voltage
mode), this LDO will supply power to V
CC
, bypassing the
main linear regulator that is powered from V
IN
. See V
AUX
Connection in the Applications Information section. Do
not exceed 16V on the V
AUX
pin.
PT
–
, PT
+
(Pin 25, 26/Pin 22, 23): Pulse Transformer Driver
Outputs. For most applications, these connect to a pulse
transformer through a series DC-blocking capacitor. The
PWM information is multiplexed together with DC power
and sent through the pulse transformer to the primary side.
The PWM signal is then decoded by the LTC3765 active
clamp forward controller and gate driver. In standalone
mode (100k or 50k resistor on MODE), the PT
+
pin has a
standard PWM signal and may be directly connected to
the gate of a primary-side MOSFET, while a reference clock
is generated on the PT
–
pin.
PGND (Pin 27/Pin 24): Gate Driver Ground Pin. Connect to
power ground at the source of the synchronous MOSFET.
V
CC
(Pin 28/Pin 25): Main V
CC
Input for All Driver and
Control Circuitry.