Datasheet

LTC3766
8
3766fa
For more information www.linear.com/LTC3766
pin FuncTions
(SSOP/QFN)
SG (Pin 1/Pin 26): Gate Drive for the Synchronous MOSFET.
FG (Pin 2/Pin 27): Gate Drive for the Forward MOSFET.
V
SEC
(Pin 3/Pin 28): Volt-Second Limit. Connect a resistor
from SW to V
SEC
, and a capacitor from V
SEC
to GND to set
the maximum volt-second product that is applied to the
main power transformer. The PWM on-time is terminated
when the V
SEC
voltage exceeds the internally generated
threshold. Tie to GND if not used.
MODE (Pin 4/Pin 1): For normal isolated applications
using the LTC3765, tie to either GND or V
CC
to set the
operating voltage to either low voltage or high voltage
modes respectively, as needed to drive the gates of the
synchronous and forward MOSFETs. For nonisolated
applications, tie to ground through either a 100k or 50k
resistor to activate standalone mode (for low voltage or
high voltage operation respectively). In this mode, the PT
+
pin may be directly connected to the gate of a primary-side
MOSFET, and a reference clock signal is generated on the
PT
–
pin. In standalone mode, the FGD pin is ignored and
the associated delay is set adaptively.
PHASE (Pin 5/Pin 2): Control Input to the Phase Selector.
This pin determines the phasing of the internal controller
CLK relative to the synchronizing signal at the FS/SYNC pin.
FB (Pin 6/Pin 3): The Inverting Input of the Main Loop
Error Amplifier. Tie to V
CC
to enable slave mode in
PolyPhase applications.
ITH (Pin 7/Pin 4): The Output of the Main Loop Error
Amplifier
. Place compensation components between the
ITH pin and GND.
RUN (Pin 8/Pin 5): Run Control Input. Holding this pin
below 1.22V will shut down the IC and reset the soft-start
and REGSD pins to 0V.
SS (Pin 9/Pin 6): Soft-Start Inputs. A capacitor to ground
sets the ramp time of the output voltage.
I
PK
(Pin 10/Pin 7): Peak Current Limit Inductor Ripple
Cancellation. This pin is used to adjust the peak current
limit based on the amount of inductor current ripple, thereby
providing a constant average output current during current
limit. Place a resistor to GND that is proportional to the main
output inductor. Leave this pin floating for constant peak
current limit. Minimize parasitic capacitance on this pin.
V
SOUT
, V
S
+
, V
S
–
(Pins 11, 12, 13/Pins 8, 9, 10): V
SOUT
is
the output of a precision, unity-gain differential amplifier.
Tie V
S
+
and V
S
–
to the output of the main DC/DC converter
to achieve true remote differential sensing. Also, V
S
+
is
used for directly sensing the output voltage for inductor
ripple cancellation. See the Applications Information sec
-
tion for details.
GND (Pin 14/Pin 11, Exposed Pad Pin 29): Signal Ground
and Kelvin Sense for SG Reverse Overcurrent. Connect to
power ground at the source of the synchronous MOSFET.
The exposed pad must be soldered to PCB ground for
rated thermal performance.
FS/SYNC (Pin 15/Pin 12): Combination Frequency Set and
Sync Pin. Tie to V
CC
to run at 275kHz. Place a resistor to
ground at this pin to set the frequency between 75kHz and
500kHz. To synchronize, drive this pin with a clock signal
to achieve PLL synchronization from 100kHz to 500kHz.
Sources 20μA of current.
REGSD (Pin 16/Pin 13): Regulator Shutdown Timer. Place
a capacitor to ground to limit the time allowed for the high
voltage linear regulator controller to operate. When the
REGSD voltage exceeds 1.21V, the linear regulator is shut
down. This pin sources 13μA of current when the linear
regulator is active.
I
S
–
(Pin 17/Pin 14): Negative Input to the Current Sense
Circuit. Connect to the negative end of a low side current
sense resistor. When using a current sense transformer,
tie this pin to V
CC
for single-ended sensing on I
S
+
with a
higher maximum trip level.
I
S
+
(Pin 18/Pin 15): Positive Input to the Current Sense
Circuit. Connect to the positive end of a low side cur-
rent sense resistor or to the output of a current sense
tr
a
nsformer.
SGD (Pin 19/Pin 16): Synchronous Gate Rising Edge Delay.
A resistor to GND sets the delay from primary gate turn-
off (PT
+
falling) to SG rising (and FG falling). This delay
is used to optimize the dead time between the turn-off of
the primary-side MOSFET and the turn-on of SG. Tie SGD
to GND to set this delay adaptively based on the falling
edge of the SW pin voltage. See Setting the Gate Driver
Delays in the Applications Information section.