Datasheet

LTC3766
49
3766fa
For more information www.linear.com/LTC3766
applicaTions inForMaTion
RUN
R1
R2
RUN/STOP
CONTROL
LTC3766
V
IN
GND
3766 F38
Figure 38. RUN/STOP Control for Standalone Applications
pin is tied to GND through either a 100k or 50k resistor
to select LV or HV operating mode.
The bias for the V
IN
pin is normally taken directly from
the input voltage of the converter. The LTC3766 contains a
current-limited internal 30V shunt to simplify applications
where V
IN
> 30V. In such applications, place a current
limiting resistor in series with the V
IN
pin calculated using:
R
VIN
=
V
IN(MAX)
– 30V
3.5mA
Note that at low V
IN
, there will be a maximum drop across
R
VIN
equal to (1.2mA) • (R
VIN
) that is due to the V
IN
pin
operating current. For proper operation, the voltage on
the V
IN
pin at low input voltage must be greater than the
rising V
CC
UVLO by at least the threshold voltage of Q
P
.
Using a MOSFET for Q
P
instead of an NPN eliminates the
base current that would otherwise add to the V
IN
operating
current. If more margin is needed at low V
IN
operation, a
Darlington transistor is another option for Q
P
.
To reduce power dissipation in Q
P
, a low voltage bias sup-
ply should be fed into the V
AUX
pin to power the bypass
LDO. This bias supply can be generated off of either the
primary or secondary of the main transformer using an
auxiliary buck or an inductor overwinding supply. During
an output overload condition, the low voltage bias supply
will collapse, causing the high voltage linear regulator
controller to be re-energized. To prevent excessive power
dissipation under this condition, place a capacitor on the
REGSD pin to limit the operating time of the high voltage
linear regulator.
The RUN pin can be used as an undervoltage lockout
(UVLO) on the converter input voltage. Direct RUN/STOP
control can be achieved by using a small NMOS on the
RUN pin as shown in Figure 38.
The resonant reset capacitor, C
RST
, serves to generate
a voltage on the SWP node during the off-time of the
primary MOSFET that resets the transformer flux on a
cycle-by-cycle basis. This capacitor is normally sized so
that the SWP voltage exactly resonates back to V
IN
at the
end of the off time with minimum V
IN
:
C
RST
≈
1
L
M
1
πf
SW
1–
V
OUT
V
IN(MIN)
N
P
N
S
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
2
–C
PAR
where L
M
is the main transformer magnetizing inductance
and C
PAR
is the total parasitic capacitance on SWP:
C
PAR
= C
OSS(PG)
+
N
S
N
P
⎛
⎝
⎜
⎞
⎠
⎟
2
C
OSS(FG)
+ C
SNUB
( )
C
PAR
includes the drain capacitance of both the PG and
FG MOSFETs as well as any snubber capacitance on the
SWB node. In reality, the presence of leakage inductance
makes the SWP node rise much faster than it otherwise
would. As a result, the optimum value for C
RST
can be 40%
to 60% higher than that calculated by the above equation.
The steady-state peak voltage on the primary and forward
MOSFETs is given by:
V
DS(PG)
= V
IN(MAX)
+
V
OUT
2f
SW
N
P
N
S
1
L
M
C
RST
+ C
PAR
( )
V
DS(FG)
=
V
OUT
2f
SW
1
L
M
C
RST
+ C
PAR
( )
If a larger value of C
RST
is used, the peak voltage stresses
can be decreased, possibly allowing the use of a MOSFET
with lower BV
DSS
rating. However, with a larger C
RST
the
SWP voltage at low V
IN
will not have time to resonate back
down to V
IN
, thereby increasing the turn-on switching
losses. In practice, some truncation of the low V
IN
reset
waveform is often tolerated to maximize the overall effi-
ciency of the converter. Note also that the peak MOSFET
voltage stress during transients can be considerably higher
,
so allow at least 30% margin above these calculated volt
-
ages. The volt-second clamp can be used to reduce the
peak voltage stress due to load transients.