Datasheet

LTC3766
45
3766fa
For more information www.linear.com/LTC3766
applicaTions inForMaTion
For the circuit of Figure 32, the overcurrent V
DS
on the
SG MOSFET is given by:
V
OC
= V
REV
R1+ R2
R2
⎛
⎝
⎜
⎞
⎠
⎟
–I
REV
R1+ R3
R1+ R2
R2
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎤
⎦
⎥
In addition to producing the desired V
OC
threshold, there
are three constraints on the selection of resistors R1, R2
and R3 that must be simultaneously met: 1) R1 and R2
must divide the maximum V
SW
plateau voltage down to
40V or less, 2) the impedance at the SW pin must be kept
as low as possible to reduce the delay in sensing the V
SW
voltage, and 3) the power dissipation in R1 and R2 must
be kept reasonably low. The last two constraints can be
met by choosing a maximum power (P
R
) to be dissipated
in the sum of R1 and R2. Typically, setting P
R
= 0.25W is a
reasonable compromise that keeps the time constant low
while not greatly impacting converter efficiency.
The selection of R1, R2 and R3 is made using the follow-
ing procedure:
1.
Calculate R1 and R2 based on a maximum power (P
R
= 0.25W) and a divider ratio that will produce exactly
40V maximum on the SW pin:
R1=
N
S
N
P
V
OUT
V
IN(MAX)
P
R
⎛
⎝
⎜
⎞
⎠
⎟
–
40V
OUT
P
R
R2=
40 • R1
N
S
N
P
V
IN
– 40
2.
If the value for V
OC
calculated using R1 and R2 from step
1) is greater than the target V
OC
value, then choose R3
such that I
REV
• R3(R1+ R2)/R2 equals the difference
between the calculated and target V
OC
values.
3. If the value for V
OC
calculated using R1 and R2 from
step 1) is less than the target value, then R3 = 0. Re-
calculate R1 and R2 based on maximum power (P
R
=
0.25W) and the desired target V
OC
value:
R1=
BI
REV
– AV
OC
+ AV
OC
+BI
REV
( )
2
– 4ABV
REV
I
REV
2AI
REV
R2=
B– AR1
A
where A = P
R
(N
P
/N
S
) and B = V
OUT
V
IN(MAX)
.
For the circuit of Figure 32, the % error in the SG overcurrent
trip can be estimated using:
ΔV
OC
=
100
V
OC
I
REV
R1+ K •R3
( )
6
⎛
⎝
⎜
⎞
⎠
⎟
2
+ K
V
REV
14
⎡
⎣
⎢
⎤
⎦
⎥
2
where K = (R1 + R2)/R2.
RC Snubbers
Most applications will make use of an RC snubber to
reduce the overshoot and ringing on the SW and SWB
pins, as shown in Figure 33. The snubber capacitor is
chosen to limit the peak voltage overshoot on SW or SWB
by absorbing the energy in the leakage inductance of the
main transformer. The snubber resistor is then chosen to
provide optimum damping so as to minimize ringing. A
larger snubber capacitor reduces the overshoot, but at the
expense of increased power dissipation in the snubber
resistor. In general, the snubber on the SWB node has far
less energy to absorb and can therefore be smaller than
that on the SW node. In some cases, the snubber on SWB
can be eliminated entirely.
The precise values needed for the RC snubbers will depend
upon the specifics of each application, and should be
optimized in the lab. Typical values for C
S1
and C
S2
range
from 1nF to 4.7nF, and R
S1
and R
S2
are typically 1Ω to
50Ω. Always use a high quality ceramic (X7R) capacitor
and resistors with a high power rating (1/4W to 1/2W) for
and an RC snubber.
R
S2
R
S1
3766 F33
V
SWB
V
SW
C
S2
C
S1
V
OUT
N
S
N
P
MAIN
XFMR
••
Figure 33. Using RC Snubbers