Datasheet

LTC3766
44
3766fa
For more information www.linear.com/LTC3766
applicaTions inForMaTion
The SG overcurrent trip should normally be targeted at
twice the maximum V
DS
of the SG MOSFET during normal
operation. This can be estimated using:
V
OC
=
R
DS(MAX)
V
OUT
f
SW
L
1–
V
OUT
V
IN(MAX)
•
N
P
N
S
⎛
⎝
⎜
⎞
⎠
⎟
where R
DS(MAX)
is the maximum R
DS(ON)
of the SG
MOSFET over temperature. This equation allows for twice
the reverse SG current that would normally occur due to
the inductor current ripple at no load. The % error in the
SG overcurrent trip can be estimated using:
ΔV
OC
=
100
V
OC
I
REV
R
SW
15
⎛
⎝
⎜
⎞
⎠
⎟
2
+
V
REV
15
⎛
⎝
⎜
⎞
⎠
⎟
2
If the above error is greater than 30%, then the V
OC
thresh-
old may need to be increased accordingly. To ensure that
the inductor doesn’t saturate prior to the SG overcurrent
t
rip, the inductor should have a saturation current such that:
I
LSAT
>
V
OC(MAX)
R
DS(MIN)
where V
OC(MAX)
is the maximum overcurrent trip based
on the above error and R
DS(MIN)
is the minimum R
DS(ON)
of the SG MOSFET over temperature.
While the circuit of Figure 30 can be used whenever the
SW node plateau voltage is 40V or less, care must be
taken to limit the current into the 50V clamp on the SW
pin due to overshoot and ringing. Figure 31 illustrates a
typical SW node waveform.
+
+
–
SGOC
3766 F32
LTC3766
SW
R3
R2
MAIN
XFMR
V
OUT
V
SW
SG
V
DS(OC)
+
–
SG
MOSFET
GND
50V
I
REV
=
LV: 103µA
HV: 42µA
V
REV
=
LV: 73mV
HV: 148mV
C
R1
•
•
Figure 32. SG Overcurrent for High V
OUT
Applications
The overshoot and ringing on the SW node is due to the
leakage inductance of main transformer, and it is worse
at full load and maximum V
IN
. The peak SW node voltage
(V
SW(PK)
) also depends heavily on the gate drive timing
as well as the RC snubber that is typically used on the SW
node. See Delay Resistor Selection: PG Turn-On Transition
and RC Snubber sections for details. Make sure that the
peak SW node voltage does not cause more than 0.2A to
flow into the SW pin:
V
SW(PK)
– 50V
R
SW
< 0.2A
The above condition is normally satisfied with reasonable
values for R
SW
and the use of an RC snubber to limit
V
SW(PK)
.
In applications where the SW node plateau voltage is
greater than 40V, it is necessary to add a divider as shown
in Figure 32.
+
+
–
SGOC
3766 F30
LTC3766
SW
R
SW
MAIN
XFMR
V
OUT
V
SW
SG
V
OC
+
–
SG
MOSFET
GND
50V
I
REV
=
LV: 103µA
HV: 42µA
V
REV
=
LV: 73mV
HV: 148mV
C
•
•
Figure 30. SG Overcurrent for Low V
OUT
Applications
0V
V
SW(PK)
PG
SW NODE
0V
3766 F31
V
IN
N
S
N
P
Figure 31. Typical SW Node Waveform