Datasheet

LTC3766
35
3766fa
For more information www.linear.com/LTC3766
applicaTions inForMaTion
SG to 1V and t
R(PG)
is the rise time of PG to 1V. The delay
time can then be chosen such that:
t
PGD
= 1.22 • t
FGD
+ t
R(FG)
+ t
F(SG)
– t
R(PG)
– t
D(PT)
The resistor from the LTC3765 DELAY pin to ground can be
selected to give this delay by using the following equation:
R
DELAY
= t
PGD
– 45ns
( )
•
1kΩ
9.5ns
In practice, the LTC3765 PG turn-on delay should be
optimized by monitoring the PG and SG waveforms. A
conservative approach is to set the PG delay to create a
dead time between SG falling and PG rising that accounts
for the delay set tolerances (typically 22% of the total delay).
A more aggressive approach takes into account the fact
that transformer leakage inductance will delay the effect
of PG turn on (i.e., SW node rising) by 75ns to 150ns or
more at full load. Also, transformer leakage inductance
mitigates the effect of a small amount of shoot-through
by slowing the rise time of the transformer current. Higher
full-load efficiency can be achieved by setting the PG turn-
on closer to SG turn-off. In addition, a shorter dead time
at PG turn-on can reduce the overshoot and ringing on
the switch node, thereby reducing the size of the required
RC snubber and its associated power loss.
While a shorter dead time at PG turn on can improve full-load
performance, care must be taken to ensure that the worst
case shoot-through at no load is well within safe limits.
Maximum Duty Cycle and Delay Phase-Out
While the PG turn-on delay time is important for reducing
turn-on switching losses, no power is transferred from the
input supply to the output load during this delay time. In
most forward converter systems, the maximum available
duty cycle is artificially limited by this delay, which then
forces a trade-off between the optimal delay time and the
maximum available duty cycle. The LTC3765 and LTC3766
implement a unique delay phase-out feature in which the
PG and FG turn-on delays are gradually reduced as the
demanded duty cycle approaches the maximum value of
79%. This feature allows a forward converter to be designed
with an optimal delay at nominal input voltage, but still
approach the maximum duty cycle at low input voltage,
thereby making better utilization of the power transformer.
Generating Secondary-Side Bias
There are five items to consider when determining the
best way to generate bias for the LTC3766 in an isolated
application:
1. The required operating current. This includes the gate
drive current for both primary and secondary MOSFETs
as well as the operating supply currents of both the
LTC3765 and the LTC3766.
2. The operating voltage needed for the MOSFET gates.
Depending on whether logic-level or standard thresh
-
old MOSFETs are used, the V
CC
operating voltage and
undervoltage lockout (UVLO) levels can be set accord-
ingly using the MODE pin. The bias supply must provide
adequate voltage to keep the L
TC3766 V
CC
pin above
its UVLO level and keep the overall supply operating at
peak efficiency.
3. Current limit operation at low output voltage. The
minimum required V
OUT
during current limit relative to
the normal operating V
OUT
has a major impact on the
design of the bias supply. The bias supply must provide
adequate voltage over this range of V
OUT
voltages.
4. The variation in input voltage. At minimum input voltage,
the bias supply must still provide enough voltage for
proper operation. At maximum voltage, the bias supply
must not generate a voltage that exceeds maximum
ratings or dissipates excessive power.
5. The potential need for a rapid hand-off from primary
to secondary control. In PolyPhase applications, it is
important to quickly transfer control to the secondary
side during start-up so that current sharing and proper
phasing can be established before the full load current
is seen at the output. By contrast, some applications
may not need to have control handed off to the second
-
ary until just prior to the output reaching its regulation
value. In all applications, however, the secondary bias
must always come up and control must be transferred
before the output reaches the regulation level.
The current that must be supplied by the secondary bias
supply can be estimated using
I
VCC
≈ (Q
GPRI
f
SW
+ 3mA)N
PT
+ Q
GSEC
f
SW
+ 18mA