Datasheet

LTC3766
24
3766fa
For more information www.linear.com/LTC3766
applicaTions inForMaTion
the active clamp PMOS, which is a potentially significant
weakness in many active clamp forward converter designs.
Since the direct flux limit functionality is implemented
in the LTC3765 on the primary side, there is nothing to
adjust on the secondary side. See the LTC3765 data sheet
for details on using this feature. Note that if the LTC3765
terminates the PG MOSFET on-time prematurely to limit
flux accumulation, the LTC3766 will sense a premature
falling on the SW node. In response, the LTC3766 will
automatically terminate the FG on-time, thereby allowing
the transformer core to reset. A premature falling on the
SW node will also occur whenever the LTC3765 has shut
down for any reason. Consequently, if the LTC3766 detects
19 consecutive premature SW node falling edges on the
SW pin, it will generate a lock fault and shut down.
Primary-Side Power MOSFET Selection
On the primary side, the peak-to-peak drive levels for
both the N-channel main switch and the P-channel active
clamp switch are determined by the voltage on the V
CC
pin of the LTC3765. This voltage is normally provided
through the pulse transformer, and is typically set in the
range of 8.5V to 12V. Note that even in applications where
a logic-level MOSFET may be used on the primary side,
the V
CC
voltage on the LTC3765 must still be in this range
for proper operation.
Selection of the N-channel MOSFET involves careful
consideration of the requirements for breakdown voltage
(BV
DSS
) and maximum drain current, while balancing the
losses associated with the on-resistance and parasitic
capacitances. In an active clamp topology, the maximum
drain voltage seen by this MOSFET is approximately:
V
DS(PG)
= 1.2 • V
CL(MAX)
where V
CL(MAX)
is the maximum active clamp voltage given
above in the Active Clamp Capacitor section. The factor
of 1.2 has been added to allow margin for ringing and
ripple on the clamp capacitor. It is important to select the
lowest possible voltage rating for this MOSFET in order
to maximize efficiency. Note that the RC snubber on the
active clamp capacitor (see Figure 10) reduces the peak
voltage stress on the primary-side MOSFET without adding
to operating losses. Also, the leakage inductance of the
main transformer at full load can cause considerable ripple
on the active clamp capacitor, pushing up the peak voltage
stress seen by the primary-side MOSFET. This ripple can
be reduced by using a larger active clamp capacitor and
a proportionally larger RC snubber capacitor. See Active
Clamp Capacitor section for more information.
Once the required BV
DSS
of the N-channel MOSFET
is known, choose a MOSFET with the lowest available
on-resistance (R
DS,ON
) that has been optimized for
switching applications (low Q
G
). In most applications,
the MOSFET will be used at a drain current that is a frac-
tion of the maximum rated current, so this rating is not
normally a consideration. The total losses associated with
the
N
-channel MOSFET at maximum output current can
be estimated using:
P
PG
=
N
P
N
S
⎛
⎝
⎜
⎞
⎠
⎟
V
OUT
I
MAX
( )
2
V
IN
1+ δ
( )
R
DS(ON)
+
N
S
N
P
⎛
⎝
⎜
⎞
⎠
⎟
V
CL
I
MAX
R
DR
Q
GD
f
SW
2V
MILLER
+ Q
GTOT
V
CC
f
SW
where δ is the temperature dependence of the on-resistance
and V
CL
is the active clamp voltage (see Active Clamp Ca-
pacitor section). R
DR
(approximately 1.7Ω for the LTC3765)
is the gate drive output resistance at the MOSFET’s miller
plateau voltage, V
MILLER
. The values of Q
DG
, Q
GTOT
and
V
MILLER
can be taken from the V
GS
versus Q
G
curve that
is typically provided in a MOSFET data sheet. Q
GD
is the
change in gate charge (Q
G
) during the region where the
V
GS
voltage is approximately constant and equal to miller
voltage, V
MILLER
. The total gate charge (Q
GTOT
) is the
gate charge when V
GS
= V
CC
. The three parts in the above
equation represent conduction losses, transition losses
and gate drive losses respectively. Highest efficiency is
obtained by selecting a MOSFET that achieves a balance
between conduction losses and the sum of transition and
gate drive losses. Note that the above equation for P
PG
is an approximation that includes assumptions. First, it
is assumed that the turn-on transition losses are rela
-
tively small because of the leakage inductance in the main
transformer. Also, it is assumed that the energy stored
in this leakage inductance at primary-switch turn-off is