Datasheet

LTC3766
15
3766fa
For more information www.linear.com/LTC3766
operaTion
inductor reflected through the transformer. This current
drives the voltage across the active clamp PMOS quickly
to 0V. Turning on the PMOS after this transition results in
minimal switching power loss. The LTC3765 active clamp
turn on delay is internally fixed to 180ns, which normally
achieves zero voltage switching on the active clamp PMOS.
On the secondary side, the turn-on delay of the forward gate
(FG) and synchronous gate (SG) MOSFETs are adjusted by
the FGD and SGD pins respectively. These delays are set
using resistors to GND so as to minimize the dead time
(when the load current is being carried by MOSFET body
diodes) while avoiding shoot-through with the primary-side
MOSFETs. A shoot-through condition exists if either the
PG and SG gates, or the AG and FG gates are high at the
same time. Note that the SG MOSFET turn-on delay has
a minimum limit that is established by the falling edge of
the SW node. The SG pin will not go high until SW has
falling below 0.5V. Refer to Delay Resistor Selection in
the Applications Information Section for more detailed
information. In standalone mode (100k or 50k resistor on
MODE) the dead time between PG and SG is set adaptively
to prevent shoot-through.
Frequency Setting and Synchronization
The LTC3766 uses a single pin to set the operating frequency
or to synchronize the internal oscillator to a reference
clock using and on-chip phase-locked loop (PLL). The
FS/SYNC pin sources a 20μA current, and it may be tied
to V
CC
for fixed 275kHz operation or have a single resistor
to GND to set the switching frequency to f
SW
= 4R
FS
. If a
clock signal (>2V) is detected at the FS pin, the LTC3766
will automatically synchronize to the falling edge of this
signal using an internal PLL.
Current Limit and Inductor Ripple Cancellation
Since the LTC3766 utilizes peak current control, the peak
inductor current is limited when the load current demand
increases above the current limit set point. The peak current
limit is established by an internal clamp on the maximum
level of the ITH voltage. The average current, however,
will be less than the peak current by an amount equal to
one-half of the inductor ripple current. During current limit,
this ripple current will change significantly with variations
in V
IN
, V
OUT
and switching frequency. Without inductor
ripple cancellation, this variation in ripple current would
also result in an average output current that changes
significantly, even though the peak current is held at a
constant value.
In order to keep the average current approximately constant
during current limit, the LTC3766 cancels the effect of the
ripple current by adjusting the value of the peak current
limit (or ITH clamp level) in proportion to the amount of
inductor ripple current. This is achieved by generating an
internal ramp that mimics the inductor current ramp, and
then adding the amplitude of this internal ramp to the ITH
clamp voltage on a cycle-by cycle basis. During the on
time, the slope of the inductor current is given by:
dI
L
dt
=
V
SW
– V
S
+
L
The LTC3766 establishes a voltage on the I
PK
pin of (V
SW
– V
S
+
)/15, which is one-fifteenth of the voltage across the
output inductor during the on-time when SW is high. By
choosing a resistor R
IPK
that is proportional to the value of
the output inductor (R
IPK
= KL), the current flowing in R
IPK
becomes proportional to the slope of the inductor current:
I
RIPK
=
V
SW
– V
S
+
15R
IPK
=
V
SW
– V
S
+
15KL
During the time when SW is high, the LTC3766 uses the
R
IPK
current to create an internal ramp by charging an
on-chip capacitor C
RIP
. The slope of this internal ramp
voltage is given by:
dV
RAMP
dt
=
I
RIPK
C
RIP
=
V
SW
– V
S
+
15KLC
RIP
The amplitude of this internal ramp is then added to the
ITH clamp level dynamically. By choosing the appropri-
ate value of R
IPK
, therefore, the average current during
current limit will be essentially independent of changes
in ripple current.
As is the case with all DC/DC converters that maintain
constant frequency operation, a cycle by cycle current
limit is only effective at duty cycles where the on time is