Datasheet

LTC3766
14
3766fa
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operaTion
has ramped up to the peak value as commanded by the
voltage on the ITH pin, the current sense comparator trips,
turning off the primary-side MOSFET. After a short delay,
the forward MOSFET is turned off and the synchronous
MOSFET is turned back on, causing the inductor current
to ramp back downwards. At the next rising edge of the
LTC3766 internal clock, the cycle repeats as the synchro
-
nous MOSFET is turned off and the forward and main
primary-side MOSFET
s are again turned on. The LTC3766
error amplifier senses the main output voltage, and adjusts
the ITH voltage to obtain the peak inductor current needed
to keep the output voltage at the desired regulation level.
In some applications, there can be considerable resistive
voltage drops between the main output voltage and the
load. To address this, the LTC3766 contains a precision
differential amplifier, which can be used to remotely sense
a load voltage as high as 15V.
Current Sensing, Slope Compensation and Blanking
The LTC3766 supports current sensing either with a current
sense resistor or with an isolated current transformer. When
using a current sense resistor, the I
S
+
and I
S
–
pins operate
differentially, and the maximum peak current threshold is
approximately 75mV. Normally, the current sense resistor
is placed in the source of the forward MOSFET to minimize
power loss. If a current transformer is used to sense the
primary-side switch current, then the I
S
–
input should be
tied to V
CC
and the I
S
+
pin to the output of the current
transformer. This causes the gain of the internal current
sense amplifier to be reduced, so that the maximum peak
current threshold is increased to approximately 1V.
As with any PWM controller that uses constant-frequency
peak current control, slope compensation is needed to
provide current-loop stability and improve noise margin.
The LTC3766 has fixed internal slope compensation. The
amount of slope has been chosen to be adequate for a
wide range of applications. Normally, the use of slope com
-
pensation would have a negative impact on the accuracy
of the
current limit, but the LTC3766 uses a proprietary
circuit to nullify the effect of slope compensation on the
current limit performance.
Since the LTC3766 current loop is sensing switch cur
-
rent, leading edge blanking is needed to avoid a current
comparator false trip due to the MOSFET turn-on current
spike.
The
LTC3766 uses the voltage on the SW pin (tied
to the drain of the synchronous MOSFET) to implement an
adaptive leading-edge blanking of approximately 180ns.
The blanking of the current comparator begins only after
the voltage on SW has risen above 1.4V. This adaptive
blanking is essential because of the potentially long delay
from the time that PT
+
rises to the time that the SW node
rises, and current begins ramping up in the output inductor.
This blanking also minimizes the need for external filtering.
Gate Driver Delay Adjustment
As in all forward converters, the main transformer core
must be properly reset so as to maintain a balanced volt-
second product and prevent saturation. This job is handled
on the primary side by the LTC3765, which features an
active clamp gate driver. The active clamp MOSFET works
together with a capacitor to generate an optimal reset volt
-
age for the main transformer. This optimal reset voltage
minimizes voltage stress on the main primary-side MOSFET
and maximizes the utilization of the power transformer
core by reducing the magnetic flux density excursion.
In general, the active clamp MOSFET is switched in a
complimentary fashion to the main primary-side MOSFET.
Since the active clamp MOSFET is a PMOS, the active clamp
gate driver (AG) and the main primary-side gate driver (PG)
voltages are therefore “in-phase,” with a programmable
overlap time set by the LTC3765 DELAY pin.
The delay time between the active clamp PMOS turn-off
and the primary switch NMOS turn-on is critical for opti
-
mizing efficiency. When the active clamp is on, the drain
of the primary NMOS, or primary switch node (SWP), is
driven to a voltage of approximately V
IN
/(1–D) by the main
transformer. When the active clamp turns off, the current
in the magnetizing inductance of the transformer ramps
this voltage linearly down to V
IN
. Power loss is minimized
by turning on the primary switch when the SWP voltage
is at a minimum. A resistor from the LTC3765 DELAY pin
to ground sets a fixed time for the PG turn-on delay.
The delay time between the primary switch turn-off and
the active clamp turn-on is substantially less critical.
When the primary switch turns off, the main transformer
leakage inductance is biased with the peak current of the