LTC3766 High Efficiency, Secondary-Side Synchronous Forward Controller Description Features n n n n n n n n n n n n n Direct Flux Limit™ Guarantees No Saturation Fast and Accurate Average Current Limit Clean Start-Up Into Pre-Biased Output Secondary-Side Control for Fast Transient Response Simple, Self-Starting Architecture Synchronous MOSFET Reverse Current Limit PolyPhase® Operation Eases High-Power Design True Remote Sense Differential Amplifier Remote Sense Reverse Protection High Voltage Linear Regul
LTC3766 Absolute Maximum Ratings (Note 1) VCC Voltage..................................................–0.3V to 12V VIN Voltage.................................................. –0.3V to 33V RUN Voltage............................................... –0.3V to 33V SW Low Impedance Source............................. –5V to 40V Current Fed........... 2mA DC or 0.2A for <1μs Into Pin* VAUX, VS+, VS –, VSOUT, NDRV Voltages....... –0.3V to 16V ITH, IS+, REGSD Voltages............................. –0.
LTC3766 Order Information LEAD FREE FINISH LTC3766EGN#PBF LTC3766IGN#PBF LTC3766HGN#PBF LTC3766MPGN#PBF LTC3766EUFD#PBF TAPE AND REEL LTC3766EGN#TRPBF LTC3766IGN#TRPBF LTC3766HGN#TRPBF LTC3766MPGN#TRPBF LTC3766EUFD#TRPBF PART MARKING* LTC3766GN LTC3766GN LTC3766GN LTC3766GN 3766 PACKAGE DESCRIPTION 28-Lead Narrow Plastic SSOP 28-Lead Narrow Plastic SSOP 28-Lead Narrow Plastic SSOP 28-Lead Narrow Plastic SSOP 28-Lead (4mm × 5mm) Plastic QFN TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –40°C to 150°C –
LTC3766 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, GND = PGND = 0V, unless otherwise noted.
LTC3766 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, GND = PGND = 0V, unless otherwise noted.
LTC3766 Typical Performance Characteristics VCC Regulator Output Voltage vs Temperature 9.0 12 11 10 9 HV MODE 8.0 7.5 LV MODE 7.0 6.5 8 7 2.90 VIN REGULATOR USING 2N3904 8.5 VCC VOLTAGE (V) VCC SUPPLY CURRENT (mA) 13 Error Amplifier Transconductance vs Temperature TRANSCONDUCTANCE (mS) 14 VCC Supply Current vs VCC Voltage 5 6 9 8 10 VCC INPUT VOLTAGE (V) 7 11 6.0 –55 –25 12 65 35 95 5 TEMPERATURE (°C) 125 0.745 55.5 97 155 125 CT MODE THRESHOLD (V) 2.
LTC3766 Typical Performance Characteristics Oscillator Frequency vs Temperature FB Voltage vs Temperature SGD Delay vs Resistance 250 599.8 1.5 200 599.4 0.5 DELAY (ns) 599.2 1.0 599.0 598.8 FS = 18.7k FS = 124k FS = VCC –0.5 –1.0 –55 –25 65 35 95 5 TEMPERATURE (°C) 125 155 598.4 –25 5 35 65 95 TEMPERARTURE (°C) 125 0 155 30 20 RSGD (kΩ) 40 50 3766 G12 SGD Delay vs Temperature FGD Delay vs Temperature 250 600 600 RSGD = 49.
LTC3766 Pin Functions (SSOP/QFN) SG (Pin 1/Pin 26): Gate Drive for the Synchronous MOSFET. FG (Pin 2/Pin 27): Gate Drive for the Forward MOSFET. VSEC (Pin 3/Pin 28): Volt-Second Limit. Connect a resistor from SW to VSEC, and a capacitor from VSEC to GND to set the maximum volt-second product that is applied to the main power transformer. The PWM on-time is terminated when the VSEC voltage exceeds the internally generated threshold. Tie to GND if not used.
LTC3766 Pin Functions (SSOP/QFN) FGD (Pin 20/Pin 17): Forward Gate Rising Edge Delay. A resistor to GND sets the delay from PT+ rising to FG rising (and SG falling). This delay is used to optimize the dead time between the turn-off of SG and the turn-on of the primary-side MOSFET. In standalone mode (100k or 50k resistor on MODE), this dead time is set adaptively and the FGD pin can be grounded. See Setting the Gate Driver Delays in the Applications Information section.
LTC3766 Block Diagram VCC SG 2.2x PEAK CURRENT COMPARATOR IS+ IS– + 29.3x – + + 2V + EA – 0.60V FB – + + C – ITH + C – 0.305V RESET DOMINANT ITRP + C – 0.2V PGND WAIT OVP RQ S SKIP DMAX ADAPTIVE BLANKING AND DELAY OVP PWM DRIVER ENCODING AND LOGIC OVERCURRENT gm = 2.7mS ERROR AMPLIFIER SWHI WAIT + SS 2.93V + C – OC BLANKING OSC AND PLL MODE FG VCC PT+ PGND VCC 1.
LTC3766 Timing Diagram PULSE ENCODED PWM VPT+ – VPT– PWM ON TIME LTC3765 AG LTC3765 PG ~ VIN 1 – DUTY CYCLE VIN SWP NODE 0V LTC3766 SG LTC3766 FG ~ VOUT 1 – DUTY CYCLE SWB NODE 0V VIN • SW NODE NS NP 0V 3766 TD01 SET BY LTC3766 FGD PIN SET BY LTC3766 SGD PIN SET BY LTC3765 DELAY PIN FIXED 180ns DELAY SW VIN+ • SWP PG AG VIN– VOUT+ • SWB PG FG FG LTC3765 AG IN+ IN– • • PT+ SW LTC3766 SG SG PT – 3766 F01 VOUT– Figure 1.
LTC3766 Operation The LTC3766 is a secondary-side PWM controller designed for use in a forward converter with active clamp reset and synchronous rectification. When used in conjunction with the LTC3765 active-clamp forward controller and gate driver, it forms a highly efficient and robust isolated power supply with a minimum number of external components.
LTC3766 Operation pin and then rapidly pre-setting the soft-start capacitor voltage to a level that corresponds to the output voltage, VOUT. This is done to provide a smooth ramp on the output voltage as control is transferred from primary to secondary, as well as to avoid any unnecessary start-up delay.
LTC3766 Operation has ramped up to the peak value as commanded by the voltage on the ITH pin, the current sense comparator trips, turning off the primary-side MOSFET. After a short delay, the forward MOSFET is turned off and the synchronous MOSFET is turned back on, causing the inductor current to ramp back downwards. At the next rising edge of the LTC3766 internal clock, the cycle repeats as the synchronous MOSFET is turned off and the forward and main primary-side MOSFETs are again turned on.
LTC3766 Operation inductor reflected through the transformer. This current drives the voltage across the active clamp PMOS quickly to 0V. Turning on the PMOS after this transition results in minimal switching power loss. The LTC3765 active clamp turn on delay is internally fixed to 180ns, which normally achieves zero voltage switching on the active clamp PMOS.
LTC3766 Operation greater than the minimum controllable on-time. Under short-circuit conditions, for example, the LTC3766 limits the current using a separate overcurrent comparator. When this overcurrent comparator is tripped, the LTC3766 generates a fault followed by a soft-start retry. This hiccup mode overcurrent protection is highly effective at minimizing power losses under short-circuit conditions.
LTC3766 Operation ated if the inputs on the differential amplifier are reversed, or if there is not enough voltage on the VIN pin to support the voltage needed on VSOUT. This is important to avoid an overvoltage condition on the output. Finally, since it is essential that the LTC3766 be in constant communication with the LTC3765, a loss of communication lock will also generate a fault.
LTC3766 Applications Information Secondary-Side Bias and Start-Up In most applications, the LTC3766 will receive its bias voltage from a supply that is generated on the secondary side. The manner in which the secondary bias is generated depends upon the output voltage as well as the variation in the input voltage of the DC/DC converter. In all applications, however, the secondary bias must always come up before the output reaches the regulation level.
LTC3766 Applications Information When used with a bias supply that is between 5V and 10V, the VCC pin can be directly connected to the bias supply as shown in Figure 4a. Note that the VIN and NDRV pins must also be connected to the bias supply for proper operation of internal circuitry. When a bias supply between 6V and 15V is available, the VAUX bypass linear regulator can be used standalone as shown in Figure 4b. In this case, proper start-up is assured by connecting the NDRV pin to VCC.
LTC3766 Applications Information control. If excessive pulse skipping occurs in applications that use a peak charge circuit to generate bias voltage, this can cause the bias supply to fall, preventing proper startup. To preclude this possibility, use the RUN pin to inhibit the LTC3766 start-up until the output voltage is at least: VOUT(ON) > 300ns NS fSWVIN(MAX) NP In PolyPhase applications, synchronization can be achieved by tying the PT – pin of the master to the FS/SYNC pin of each slave.
LTC3766 Applications Information Be careful to keep these divider resistors very close to the FB pin to minimize the trace length and noise pick-up on the sensitive FB signal. Using a low resistance (<2k) for the output voltage divider also minimizes noise on the FB pin. If the remote sense amplifier is used, then the divider should be placed between the VSOUT pin and GND. See the Remote Sensing section for details.
LTC3766 Applications Information transients when operating at minimum input voltage. A value for DMAX of 0.65 to 0.70 is appropriate for most applications. Having selected a particular transformer, calculate the copper losses associated with the transformer winding. These losses are highest when operating at maximum duty cycle and full load.
LTC3766 Applications Information cause oscillations under certain conditions. To avoid the problems associated with this resonance, always use an RC snubber in parallel with the clamp capacitor as shown in Figure 9. The values for this RC snubber can then be calculated using: ACTIVE CLAMP VOLTAGE NORMALIZED TO 50% DUTY CYCLE 1.6 1.5 1.4 1.3 1.2 RCS = 1.1 1.0 0.9 20 30 40 50 60 DUTY CYCLE (%) 70 80 3766 F08 Figure 8.
LTC3766 Applications Information the active clamp PMOS, which is a potentially significant weakness in many active clamp forward converter designs. Since the direct flux limit functionality is implemented in the LTC3765 on the primary side, there is nothing to adjust on the secondary side. See the LTC3765 data sheet for details on using this feature. Note that if the LTC3765 terminates the PG MOSFET on-time prematurely to limit flux accumulation, the LTC3766 will sense a premature falling on the SW node.
LTC3766 Applications Information completely recovered by the active clamp capacitor. For most applications, these assumptions are valid and the above equation is a good approximation. The active clamp P-channel MOSFET has the same BVDSS requirement as that of the N-channel MOSFET. Since the P-channel MOSFET only handles the magnetizing current, it is normally much smaller (typically a SOT package).
LTC3766 Applications Information voltage on the VCC pin of the LTC3766. For the synchronous MOSFET, the power loss is approximately: ⎛ N V ⎞ 2 PSG = ⎜ 1– P OUT ⎟ (IMAX ) (1+ δ )RDS(ON) ⎝ NS VIN ⎠ +QGTOT VBIAS fSW The power losses for the synchronous and forward MOSFET are generally dominated by conduction losses. For both of the above power loss equations, it is assumed that the dead time (when the MOSFET body diode is conducting) has been minimized.
LTC3766 Applications Information Input Capacitor/Filter Selection In applications with a low impedance source, or where there the input voltage is relatively low, a simple capacitive input filter is generally suitable. This capacitor needs to have a very low ESR and must be rated to handle a worst-case RMS input current of: ⎛ N ⎞ IOUT(MAX) IC(RMS) = ⎜ S ⎟ 2 ⎝ NP ⎠ Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life.
LTC3766 Applications Information The damping inductor LD does not carry the DC input current. However, to ensure adequate attenuation during large transients, choose an inductor whose saturation current is at least: ⎛ VOUTIOUT(MAX) ⎞ ISAT(LD) ≥ 0.6 ⎜ VIN(MIN) ⎟⎠ ⎝ Output Capacitor Selection The selection of COUT is driven by the effective series resistance (ESR) and the resulting output voltage ripple. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering.
LTC3766 Applications Information transformer. This causes the gain of the internal current sense amplifier to be reduced, so that the maximum peak current voltage is increased to approximately 1V. The current transformer connections are shown in Figure 12. CURRENT TRANSFORMER + VIN • • SF = DCT IS+ RCAL 1k RSENSE CFL VCC LTC3766 GND NP • • IS– 3766 F12 NS voltage and comparing it to the output inductor current.
LTC3766 Applications Information • For resistor sense mode, place a resistor on the IPK pin that is chosen using: VOUT VSW • LTC3766 VS+ MAIN XFMR SW VS– IPK VSOUT RIPK RLOAD 3766 F14a Figure 14a. Setting the Average Current Limit (RIPK) • LTC3766 MAIN XFMR VS+ SW VS– IPK VSOUT RIPK 3766 F14 Figure 14b. Setting RIPK with No Differential Amplifier • MAIN XFMR R1 LTC3766 VSOUT SW R2 160k VS– IPK RIPK 120k VS+ KRLIPK N • P (1.
LTC3766 Applications Information Estimating the Average Current Limit Accuracy The accuracy of the average current limit depends on the LTC3766 specifications together with a number of application circuit parameters as well as parasitics. Consequently, it is very difficult to precisely calculate the average current limit accuracy. This accuracy can be estimated, however, by carefully considering the three primary sources of error: 1.
LTC3766 Applications Information In addition to being set to minimize the dead time between SG falling and PG rising, the FG rising delay should also be adjusted to ensure that the drain of the forward switch (SWB) is close to 0V when the switch is turned on, which minimizes switching loss. When the LTC3765 active clamp switch turns off, the drain voltage of the primary switch (SWP) decreases linearly from VIN/(1 – D) to VIN, where D is the duty cycle.
LTC3766 Applications Information Another important consideration in setting the SGD delay is the prevention of SWP collapse due to excessive FG turn-off delay. After PG turn-off, the SWP node is quickly driven high by the transformer leakage to a level of approximately VIN/(1 – D). Ideally, it should remain at this voltage as FG turns off, SG turns on, and then AG turns on.
LTC3766 Applications Information the delays should initially be selected so that they are long, while keeping in mind that the FG delay must be less than the PG delay to prevent potentially damaging PG/SG cross-conduction. As a first pass, use a 75k resistor from FGD to ground for a 415ns delay and 60k resistor from DELAY to ground for a 622ns delay. The SWP and SWB waveforms should appear as shown in Figure 18.
LTC3766 Applications Information SG to 1V and tR(PG) is the rise time of PG to 1V. The delay time can then be chosen such that: tPGD = 1.22 • tFGD + tR(FG) + tF(SG) – tR(PG) – tD(PT) The resistor from the LTC3765 DELAY pin to ground can be selected to give this delay by using the following equation: RDELAY = ( tPGD – 45ns ) • 1kΩ 9.5ns In practice, the LTC3765 PG turn-on delay should be optimized by monitoring the PG and SG waveforms.
LTC3766 Applications Information where QGPRI is the total gate charge of all primary-side MOSFETs, QGSEC is the total gate charge of all secondaryside MOSFETs, and NPT is the turns ratio of the pulse transformer. Note that the primary-side current is scaled by the turns ratio of the pulse transformer. The 18mA constant in the above equation includes typical gate drive switching current as well as losses associated with the pulse transformer.
LTC3766 Applications Information When calculating tOUT, use a value for VHO that corresponds to the target output voltage for control hand-off, typically one-half the normal regulation level or less. If tOUT is less than tBIAS, then the LTC3765 soft-start capacitor value should be increased. Note that these equations are approximations and the actual times will vary somewhat with circuit parameters.
LTC3766 Applications Information At maximum VIN, there may be considerable power dissipation in the linear regulator pass device Q1. This power can be calculated using PQ1 = (VBIAS – VCC)IVCC For Figure 24 the output is given by: VBUCK = VOUT NAUX – 0.5 NS In applications where the peak charge and high voltage linear regulator must operate continuously, transistor Q1 must be capable of dissipating this power without excessive temperature rise.
LTC3766 Applications Information The buck bias winding can also be used standalone without the peak charge supply, as shown in Figure 25. This is sometimes done in applications where the peak charge circuit is impractical, such when the VIN voltage has a wide range. When using the buck bias supply standalone, particular care must be taken to ensure that the bias output comes up more quickly than the main output, and that there is adequate bias voltage immediately after control handoff.
LTC3766 Applications Information A useful variant of the inductor over-winding bias supply is shown in Figure 27, where a discrete transformer TOW has been used instead of an additional winding on the main inductor LF . This is often more convenient because standard parts can readily be used. in Figures 23 and 24). This enables a low power pass transistor to be used. See Linear Regulator Operation for more information on using the REGSD feature.
LTC3766 Applications Information as the communication link between the secondary-side controller and the primary-side gate driver, as shown in Figure 28. In addition, LTC3765 contains a bridge rectifier that extracts bias power from the pulse transformer, which it then uses to drive the gates of the primary-side MOSFETs.
LTC3766 Applications Information because no amount of tweaking to the ITH components can cancel their effect. Also, any theoretical analysis of loop response only considers first order non-ideal component behavior. Consequently, it is important that a final stability check be made with production layout and components. Stabilizing the voltage loop of the LTC3766 is accomplished by using the error amp to provide a gain from VOUT to ITH that compensates for the control to output gain from ITH to VOUT.
LTC3766 Applications Information associated with the dominant pole. A high frequency pole is also added to reduce noise and provide attenuation of the output voltage ripple. Note that significant gain at the switching frequency in this compensation network can cause instabilities. The network of Figure 29 has a DC gain of: ADC2 = R2 gmREA R2+R3 where REA = 5MΩ is the output resistance of the error amplifier and gm = 2.7mS is the transconductance.
LTC3766 Applications Information The SG overcurrent trip should normally be targeted at twice the maximum VDS of the SG MOSFET during normal operation. This can be estimated using: PG 0V VSW(PK) RDS(MAX)VOUT ⎛ VOUT NP ⎞ VOC = 1– • ⎟ ⎜ V fSWL ⎝ IN(MAX) NS ⎠ SW NODE where RDS(MAX) is the maximum RDS(ON) of the SG MOSFET over temperature. This equation allows for twice the reverse SG current that would normally occur due to the inductor current ripple at no load.
LTC3766 Applications Information For the circuit of Figure 32, the overcurrent VDS on the SG MOSFET is given by: ⎡ ⎛ R1+R2 ⎞ ⎛ R1+R2 ⎞ ⎤ VOC = VREV ⎜ –IREV ⎢R1+R3 ⎜ ⎟ ⎝ R2 ⎠ ⎝ R2 ⎟⎠ ⎥⎦ ⎣ In addition to producing the desired VOC threshold, there are three constraints on the selection of resistors R1, R2 and R3 that must be simultaneously met: 1) R1 and R2 must divide the maximum VSW plateau voltage down to 40V or less, 2) the impedance at the SW pin must be kept as low as possible to reduce the delay in sens
LTC3766 Applications Information Remote Sensing the input stage of the differential amplifier. If the input stage is saturated, the LTC3766 forces the VSOUT pin to 0V. In applications where the differential amplifier is not needed, connect the inputs as shown in either Figure 14b or Figure 15. The LTC3766 contains a precision differential amplifier for use in remote sensing applications.
LTC3766 Applications Information switched once. The SSFLT pin currents then decrease to their nominal values. This ensures that all phases begin their asynchronous, open-loop start-up at nearly the same time. On the secondary side, the SS pins from all phases are interconnected as well. This prevents any one phase from starting until all phases have adequate bias voltage and have detected switching on their respective SW pins.
LTC3766 Applications Information Volt-Second Clamp When used in applications with the LTC3765, direct flux limit will guarantee that no saturation occurs on the main transformer. Consequently, there is no need to use a voltsecond clamp in applications that have the direct flux limit feature. In applications where the LTC3766 is used standalone, however, the volt-second clamp can be used as a failsafe to prevent excessive volt-seconds from being applied to the main transformer during the PWM on-time.
LTC3766 Applications Information pin is tied to GND through either a 100k or 50k resistor to select LV or HV operating mode. The bias for the VIN pin is normally taken directly from the input voltage of the converter. The LTC3766 contains a current-limited internal 30V shunt to simplify applications where VIN > 30V. In such applications, place a current limiting resistor in series with the VIN pin calculated using: R VIN = VIN(MAX) – 30V 3.
LTC3766 Applications Information The setting of the gate drive timing for a resonant reset converter is simplified by the adaptive delays featured in the LTC3766. When standalone mode is active (100k or 50k on MODE), the FGD pin is ignored, and the associated dead time between SG turn-off and PG turn-on is controlled adaptively. In this mode, LTC3766 delays the PG turn-on until after the SG pin has fallen below approximately 0.5V.
LTC3766 Applications Information 2. Plan the power/ground routing carefully. Know where the large load switching current is coming from and going to. Maintain three separate planes if possible: signal ground (GND pin), power ground (PGND pin) and power stage ground. The power ground plane should be connected with a single via to the source of the SG MOSFET. The signal ground plane should be connected with a single via to the source of the SG MOSFET for accurate VDS sensing.
LTC3766 Typical Applications +VIN 36V TO 72V • 2.2µF 100V ×3 FDMS86201 33nF 200V T1 6:2 • +VOUT 5V 15A 1nF 100V BSC0901NS 100nF 200V 15mΩ 168Ω 1/2W –VIN L1 1.4µH 1µF 10V 220µF 6.3V ×2 L1: PULSE PA1392.152 T1: PULSE PA0810 T2: PULSE PA0297 SiR414DP 10Ω 1/4W 3mΩ 2W –VOUT Si3440DV Si3437DV (SOT23) 200k 100Ω 2.2nF 250V 330pF 1Ω 365k IS+ IS– NDRV PG 0.1µF ISMAG IN+ RUN 15.0k AG VCC 220pF LTC3765 4.7µF SSFLT RCORE 33nF DELAY 10.5k 100Ω • T2 2:1 1.
LTC3766 Typical Applications 9V-36V to 24V/4.2A Active Clamp Isolated Forward Converter L1 0.47µH +VIN 9V TO 36V • T3 10µF 50V ×3 10µF 50V • D3 IS+ 2T 1.2k 1/8W • T1 L2 58µH • • 24Ω 1W 8T 4T 150pF 250V D4 Q1 –VIN 4mΩ 1W ES1PD 0.33Ω 1/8W 100Ω 100Ω 2.2nF D1 100k 2N7002 1µF 1nF 6.19k 14.3k +VIN 147k IS– 15Ω 1/8W 1µF 100V L3 680µH 2.2µF 3.65Ω IS+ 1nF AG VCC 0.1µF IN+ LTC3765 DELAY IN– RCORE FS/UV 10k 0.1µF 1µF T2 2.5:2 • • VAUX NDRV +VOUT FCX491A 4.
LTC3766 Typical Applications 18V-75V to 12V/12.5A Active Clamp Isolated Forward Converter L1 1.8µH +VIN 18V TO 75V 2.2µF 100V • T3 2.2µF 100V ×3 • D3 IS+ 4T 1.2k 1/8W • T1 L2 11µH • 51Ω 1/2W 4T 1.82k 1/4W ES1PD Q2 ES1PD 0.75Ω 1/8W –VIN 100Ω 1nF D1 200k FDC2512 1µF 1nF 6.19k 13.3k +VIN 61.9k IS– SW FG 5.11Ω 1/8W 100Ω +VIN IS+ 1nF 10k LTC3766 33nF NPO D2 NDRV AG VCC 0.1µF IN+ 0.1µF LTC3767 DELAY VCC SS IS– MODE PT+ • 16.9k 2.2nF 250VAC 33nF 15k SSFLT 60.
LTC3766 Typical Applications 36V-60V to 32V at 10A 320W Isolated P/A Power Supply L1 1.8µH +VIN 36V TO 60V • T3 2.2µF 100V ×3 2.2µF 100V • D6 IS+ 4T 330Ω 1/8W • T1 L2 10µH • • 2T D4 –VIN 33nF 200V 4mΩ 1W ES1PD 0.56Ω 1/8W 100Ω 100Ω 1.5nF D1 200k FDC2512 1µF 1nF 13k 8.25k +VIN 66.5k L3 680µH 4.7µF 10k 1nF AG VCC 0.1µF IN+ LTC3765 DELAY IN– RCORE FS/UV 33nF NPO D2 0.1µF • 220pF VCC SS IS– • 604Ω FB 330pF 1k PT– 27.4k FCX491A 1µF IS+ PT+ 27.4k 2.
LTC3766 Typical Applications 36V-60V to 14V at 25A 350W Isolated Bus Converter L1 1.8µH +VIN 36V TO 60V • T3 2.2µF 100V ×3 2.2µF 100V • 4mΩ 1W ES1PD 0.68Ω 1/8W 100Ω 100Ω 1nF 1µF 1nF 14k 11k +VIN 66.5k 1.00k 1/8W 3T IS– 165Ω 1/8W 0.22µF 250V 33nF 200V SW FG 1nF LTC3766 3.3nF 33nF NPO D2 NDRV AG VCC 0.1µF IN+ LTC3767 DELAY IN– RCORE FS/UV 0.1µF 27.4k 15.0k 60.4k 150k 10nF 4.
LTC3766 Package Description GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B) .386 – .393* (9.804 – 9.982) .045 ±.005 28 27 26 25 24 23 22 21 20 19 18 17 1615 .254 MIN .033 (0.838) REF .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0250 BSC .0165 ±.0015 1 RECOMMENDED SOLDER PAD LAYOUT .015 ±.004 × 45° (0.38 ±0.10) .0075 – .0098 (0.19 – 0.25) 2 3 4 5 6 7 8 .0532 – .0688 (1.35 – 1.75) 9 10 11 12 13 14 .004 – .0098 (0.102 – 0.
LTC3766 Package Description UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 ±0.05 4.50 ±0.05 3.10 ±0.05 2.50 REF 2.65 ±0.05 3.65 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.50 REF 4.10 ±0.05 5.50 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 (2 SIDES) 0.75 ±0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 ±0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.
LTC3766 Revision History REV A DATE DESCRIPTION 6/13 Switch polarity between IS+ and IS– in Figure 11 PAGE NUMBER 28 3766fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.
LTC3766 Typical Application 36V-72V to 3.3V/20A Nonisolated Resonant-Reset Forward Converter VIN 36V TO 72V L1 0.85µH T1 L1: PULSE PA1294.910NL L2: COOPER SD25-102 T1: PULSE PA0810.006NL 2.2µF 100V ×3 12T 1.5nF 200V NPO BSC320N20NS3 BAT54 15mΩ 1W 100Ω 100Ω 6T • • 2T 1nF 50V 2.4Ω 1/4W 100µF + 6.3V ×2 • 220µF 6.3V BSC0901NS L2 1mH 1µF VOUT 3.3V 20A BSC0901NS BAT54 330pF 210k 16.5k 1/4W IS+ PT+ IS– VAUX FG VS– VIN Si2328DS (SOT23) 1nF 7.87k NDRV 0.
