Datasheet

LTC3765
17
3765fb
For more information www.linear.com/LTC3765
APPLICATIONS INFORMATION
The above equation assumes that there is no load cur-
rent, which is the worst-case condition for output voltage
rise.
If t
OUT
is less than t
BIAS
, then the soft-start capacitor
value should be increased. Note that these equations are
approximations and the actual times will vary somewhat
with circuit parameters.
Gate Drivers
The active clamp gate driver (AG) and the primary switch
gate driver (PG) are “in-phase,” with a programmable
overlap time set by the DELAY pin. Traditionally in active
clamp drivers, the AG driver must be level-shifted as shown
in the circuit in Figure 7a to drive the active clamp PMOS
gate from approximately V
D
to –V
CC
+ V
D
, where V
D
is
the forward voltage drop across the Schottky diode D
AG
.
A silicon diode can be used instead of a Schottky barrier
diode; however, the forward voltage of the diode does
subtract from the available gate drive of the active clamp
PMOS. This is particularly important at the minimum V
CC
UVLO falling threshold.
The resistor, R
AG
, ensures that the active clamp PMOS
is off when not being driven. The active clamp level-shift
circuit components can be chosen with few
constraints. The
time
constant formed by R
AG
and C
AG
should be designed
to be substantially longer than the switching period of the
controller. A 0.1µF capacitor for C
AG
and a 10k resistor for
R
AG
result in a 1ms time constant, which provides suf-
ficient margin
for the 75kHz to 500kHz frequency range
available in the LTC3766.
Alternatively, the active clamp PMOS source can be returned
to the V
CC
supply bypass capacitor, as shown in Figure7b.
In this configuration, the level-shift circuit comprised of
C
AG
, D
AG
and R
AG
is not needed. The AG output drives the
gate of the PMOS between V
CC
and ground.
Figure 7a. Traditional AG and PG Driver Configuration
Figure 7b. Alternative AG and PG Driver Configuration
••
3765 F07a
V
IN
PRIMARY
SWITCH
NMOS
ACTIVE
CLAMP
PMOS
PG
AG
MAIN
TRANSFORMER
C
CLAMP
I
SMAG
D
AG
C
AG
R
AG
C
SN
R
SN
R
MAG
••
3765 F07b
V
IN
PRIMARY
SWITCH
NMOS
ACTIVE
CLAMP
PMOS
PG
AG
V
CC
MAIN
TRANSFORMER
C
CLAMP
C
SN
R
SN
C
VCC
I
SMAG
R
MAG
Unlike the configuration in Figure 7a, the main transformer
leakage current spike and magnetizing current return to
the V
CC
bypass capacitor. The V
CC
capacitor should be
increased to prevent excessive ripple on the supply and
a low impedance plane should be used to route V
CC
. The