Datasheet

LTC3736-2
7
37362fb
PIN FUNCTIONS
FUNCTIONAL DIAGRAM
select. For auxiliary winding applications, connect to a
resistor divider from the auxiliary output. To synchronize
with an external clock using the PLL, apply a CMOS compat-
ible clock with a frequency between 250kHz and 850kHz.
To select pulse-skipping operation at light loads, tie this
pin to V
IN
. Grounding this pin selects forced continuous
operation, which allows the inductor current to reverse.
When synchronized to an external clock, pulse-skipping
operation is enabled at light loads.
BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate
Drive Output. These pins drive the gates of the external
N-channel MOSFETs. These pins have an output swing
from PGND to SENSE
+
.
SENSE1
+
/SENSE2
+
(Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers
the gate drivers. Normally connected to the source of the
external P-channel MOSFET.
SW1/SW2 (Pins 22, 10/Pins 1, 13): Switch Node Con-
nection to Inductor. Also the negative input to differential
peak current comparator and an input to the reverse cur-
rent comparator. Normally connected to the drain of the
external P-channel MOSFETs, the drain of the external
N-channel MOSFET, and the inductor.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
Select Maximum Peak Sense Voltage Threshold. These
pins select the maximum allowed voltage drop between
the SENSE
+
and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie to V
IN
, GND or fl oat to select 345mV, 167mV, or 240mV,
respectively.
V
FB1
/V
FB2
(Pins 24, 7/Pins 3, 10): Feedback Pins. Re-
ceives the remotely sensed feedback voltage for its con-
troller from an external resistor divider across the output.
–
+
–
+
–
+
–
+
SHDN
0.6V
V
REF
EXTSS
0.7μA
CLK1
CLK2
FCB
0.54V
V
FB1
V
FB2
FCB
0.6V
SLOPE1
SLOPE2
RUN/SS
V
IN
C
VIN
V
IN
(TO CONTROLLER 1, 2)
R
VIN
SYNC/FCB
PLLLPF
VOLTAGE
REFERENCE
UNDERVOLTAGE
LOCKOUT
PHASE
DETECTOR
SYNC DETECT
SLOPE
COMP
VOLTAGE CONTROLLED
OSCILLATOR
t
SEC
= 1ms
INTSS
PGOOD
SHDN
OV1
UV1
UV2
OV2
37362 FD
(Common Circuitry)
(QFN/SSOP Package)