Datasheet

LTC3736-2
6
37362fb
PIN FUNCTIONS
I
TH1
/I
TH2
(Pins 1, 8/Pins 4, 11): Current Threshold and
Error Amplifi er Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves as
the lowpass fi lter point for the phase-locked loop. Normally
a series RC is connected between this pin and ground.
When not synchronizing to an external clock, this pin serves
as the frequency select input. Tying this pin to GND selects
300kHz operation; tying this pin to V
IN
selects 750kHz
operation. Floating this pin selects 550kHz operation.
SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves
as the ground connection for most internal circuits.
V
IN
(Pin 5/Pin 8): Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Exter-
nally fi ltering this pin with a lowpass RC network (e.g.,
R = 10Ω, C = 1μF) is suggested to minimize noise pickup,
especially in high load current applications.
TRACK (Pin 6/Pin 9): Tracking Input for Second Controller.
Allows the start-up of V
OUT2
to track that of V
OUT1
accord-
ing to a ratio established by a resistor divider on V
OUT1
connected to the TRACK pin. For one-to-one tracking of
V
OUT1
and V
OUT2
during start-up, a resistor divider with
values equal to those connected to V
FB2
from V
OUT2
should
be used to connect to TRACK from V
OUT1
.
PGOOD (Pin 9/Pin 12): Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (V
FB1
, V
FB2
) is
not within ±13.3% of its nominal set point.
PGND (Pins 12, 16, 20, 25/Pins 15, 19, 23): Power
Ground. These pins serve as the ground connection for
the gate drivers and the negative input to the reverse cur-
rent comparators. The Exposed Pad must be soldered to
PCB ground.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
External Soft-Start Input. Forcing this pin below 0.65V shuts
down the chip (both channels). Driving this pin to V
IN
or
releasing this pin enables the chip, using the chip’s internal
soft-start. An external soft-start can be programmed by
connecting a capacitor between this pin and ground.
TG1/TG2 (Pins 17, 15/Pins 18, 20): Top (PMOS) Gate
Drive Output. These pins drive the gates of the external
P-channel MOSFETs. These pins have an output swing
from PGND to SENSE
+
.
SYNC/FCB (Pin 18/Pin 21): This pin performs three func-
tions: 1) auxiliary winding feedback input, 2) external
clock synchronization input for phase-locked loop, and
3) pulse-skipping operation or forced continuous mode
(QFN/SSOP Package)
TYPICAL PERFORMANCE CHARACTERISTICS
Undervoltage Lockout Threshold
vs Temperature
Shutdown Quiescent Current
vs Input Voltage
RUN/SS Start-Up Current
vs Input Voltage
T
A
= 25°C, unless otherwise noted.
TEMPERATURE (°C)
–60
INPUT (V
IN
) VOLTAGE (V)
2.30
2.40
100
37362 G16
2.20
2.10
–20
20
60
–40
0
40
80
2.50
2.25
2.35
2.15
2.45
V
IN
RISING
V
IN
FALLING
INPUT VOLTAGE (V)
2
0
SHUTDOWN CURRENT (μA)
2
6
8
10
20
14
4
6
7
37362 G17
4
16
18
12
35
8
9
10
RUN/SS = 0V
INPUT VOLTAGE (V)
2
RUN/SS PIN PULL-UP CURRENT (μA)
0.5
0.6
0.7
10
37362 G18
0.4
0.3
0
0.1
4
6
8
3
5
7
9
0.2
0.9
0.8
RUN/SS = 0V