Datasheet

LTC3736-2
23
37362fb
APPLICATIONS INFORMATION
Figures 13. LTC3736-2 Layout Diagram
related to the stability of the closed-loop system and will
demonstrate the actual overall supply performance. For
a detailed explanation of optimizing the compensation
components, including a review of control loop theory,
refer to Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10μF capacitor would require a 250μs rise time,
limiting the charging current to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3736-2. These items are illustrated in the layout
diagram of Figure 13. Figure 14 depicts the current wave-
forms present in the various branches of the 2-phase dual
regulator.
1. The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small
as possible and isolated as much as possible from the
power loop of the other channel. Ideally, the drains of
the P- and N-channel FETs should be connected close
to one another with an input capacitor placed across
the FET sources (from the P-channel source to the N-
channel source) right at the FETs. It is better to have
two separate, smaller valued input capacitors (e.g., two
10μF—one for each channel) than it is to have a single
larger valued capacitor (e.g., 22μF) that the channels
share with a common connection.
2. The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor divid-
ers, I
TH
compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the
input and output capacitors and the source of the N-
channel MOSFET. Each channel should have its own
power ground for its power loop (as described above
in item 1). The power grounds for the two channels
should connect together at a common point. It is most
important to keep the ground paths with high switching
currents away from each other.
The PGND pins on the LTC3736-2 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3. Put the feedback resistors close to the V
FB
pins. The
trace connecting the top feedback resistor (R
B
) to
the output capacitor should be a Kelvin trace. The I
TH
compensation components should also be very close
to the LTC3736-2.
4. The current sense traces (SENSE
+
and SW) should
be Kelvin connections right at the P-channel MOSFET
source and drain.
5. Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channel’s feedback
resistors, I
TH
compensation components, and the cur-
rent sense pins (SENSE
+
and SW).
SW1
IPRG1
V
FB1
I
TH1
IPRG2
PLLLPF
SGND
V
IN
TRACK
V
FB2
I
TH2
PGOOD
SENSE1
+
PGND
BG1
SYNC/FCB
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
+
SW2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LTC3736EGN-2
+
+
C
OUT1
C
OUT2
C
VIN1
C
VIN
V
OUT1
V
OUT2
BOLD LINES INDICATE HIGH CURRENT PATHS
37362 F13
L1
L2
MN1 MP1
MN2 MP2
V
IN
C
VIN2