Datasheet

LTC3736-2
11
37362fb
OPERATION
higher than forced continuous mode. During start-up or
a short-circuit condition (V
FB1
or V
FB2
≤ 0.54V), the
LTC3736-2 operates in pulse-skipping mode (no current
reversal allowed), regardless of the state of the SYNC/
FCB pin.
Short-Circuit Protection
When an output is shorted to ground (V
FB
< 0.12V), the
switching frequency of that controller is reduced to one
fi fth of the normal operating frequency. The other controller
is unaffected and maintains normal operation.
The short-circuit threshold on V
FB2
is based on the smaller
of 0.12V and a fraction of the voltage on the TRACK pin.
This also allows V
OUT2
to start up and track V
OUT1
more
easily. Note that if V
OUT1
is truly short-circuited (V
OUT1
=
V
FB1
= 0V), then the LTC3736-2 will try to regulate V
OUT2
to 0V if a resistor divider on V
OUT1
is connected to the
TRACK pin.
Output Overvoltage Protection
As a further protection, the overvoltage comparator (OV)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the V
FB
pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
Frequency Selection and Phase-Locked Loop (PLLLPF
and SYNC/FCB Pins)
The selection of switching frequency is a tradeoff between
effi ciency and component size. Low frequency opera-
tion increases effi ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3736-2’s controllers
can be selected using the PLLLPF pin.
If the SYNC/FCB is not being driven by an external
clock source, the PLLLPF can be fl oated, tied to V
IN
or tied to SGND to select 550kHz, 750kHz or 300kHz,
respectively.
A phase-locked loop (PLL) is available on the LTC3736-2
to synchronize the internal oscillator to an external clock
source that is connected to the SYNC/FCB pin. In this
case, a series RC should be connected between the
PLLLPF pin and SGND to serve as the PLL’s loop fi lter.
The LTC3736-2 phase detector adjusts the voltage on the
PLLLPF pin to align the turn-on of controller 1’s external
P-channel MOSFET to the rising edge of the synchronizing
signal. Thus, the turn-on of controller 2’s external P-chan-
nel MOSFET is 180 degrees out-of-phase with the rising
edge of the external clock source.
The typical capture range of the LTC3736-2’s phase-locked
loop is from approximately 200kHz to 1MHz, and is guaran-
teed over temperature to be between 250kHz and 850kHz.
In other words, the LTC3736-2’s PLL is guaranteed to lock
to an external clock source whose frequency is between
250kHz and 850kHz.
Dropout Operation
When the input supply voltage (V
IN
) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle) decreases. This reduction means that the P-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the I
TH
pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%, i.e., DC. The output volt-
age will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
input voltage levels, an undervoltage lockout is incorpo-
rated in the LTC3736-2. When the input supply voltage
(V
IN
) drops below 2.3V, the external P- and N-channel
MOSFETs and all internal circuitry are turned off except
for the undervoltage block, which draws only a few
microamperes.
(Refer to Functional Diagram)