Datasheet

LTC3735
7
3735fa
TYPICAL PERFORMANCE CHARACTERISTICS
V
RUN/SS
Shutdown Latch
Thresholds vs Temperature Load Step (Figure 14) VID Transition (Figure 14)
PIN FUNCTIONS
(G/UHF)
TEMPERATURE (°C)
–50 –25
0
SHUTDOWN LATCH THRESHOLDS (V)
0.5
1.5
2.0
2.5
75 10050
4.5
3735 G21
1.0
0 25 125
3.0
3.5
4.0
LATCH ARMING
LATCHOFF
THRESHOLD
I
OUT
10A/DIV
V
OUT
100mV/DIV
20s/DIV
32A
7.2A
1.364V
1.230V
3735 G22
VIDs
V
OUT
200mV
/DIV
50s/DIV
1
0
1.356V
0.844V
3735 G23
PGOOD
2V/DIV
V
FB
(Pin 1/Pin 37): Input to the error amplifier that com-
pares the feedback voltage to the internal 0.6V reference
voltage.
DPRSLPVR (Pin 2/Pin 38): Deeper Sleep State Input.
When the signal to this pin is high, the voltage regulator
enters deeper sleep state and its output is determined
by the parallel resistor value of RDPRSLP and RDPSLP.
When the signal is low, the voltage regulator exits deeper
sleep state.
FREQSET (Pin 3/Pin 1): Frequency Set Pin. Apply a DC
voltage between 0V and 5V to set the operating frequency
of the internal oscillator. This frequency is the switching
frequency of each phase.
PSIB (Pin 4/Pin 2): Power Status Indicator Input. When
the signal to this pin is high, both channels operate in fully
synchronous switching mode for fastest transient and
lowest ripple. When the signal is low, controller enters
power saving mode, providing high efficiency at light load.
V
OA
+
, V
OA
–
(Pins 5, 6/Pins 3, 4): Inputs to the Internal
Operational Amplifier.
OAOUT (Pin 7/Pin 5): Output of the Internal Operational
Amplifier.
STP_CPUB (Pin 8/Pin 6): Deep Sleep State Input. When the
signal to this pin is low, the voltage regulator enters deep
sleep state and its output voltage is a certain percentage
lower than the VID commands. This offset percentage is
set by the resistor connected to the RDPSLP pin. When
the signal to this pin is high, the voltage regulator exits
deep sleep state.
SGND (Pin 9/Pin 7): Signal Ground. This pin is common
to both controllers. Route separately to the PGND pin.
SENSE1
+
, SENSE2
+
(Pins 10,12/Pins 8, 9): The (+) Input
to Each Differential Current Comparator. The I
TH
pin voltage
and built-in offsets between SENSE
–
and SENSE
+
pins in
conjunction with R
SENSE
set the current trip threshold.
SENSE1
–
, SENSE2
–
(Pins 11,13/Pins 10, 11): The (–)
Input to Each Differential Current Comparator.
RDPRSLP (Pin 14/Pin 12): Deeper Sleep State Resistor
Pin. Connect a resistor from this pin to V
OA
+
. This resis-
tor in conjunction with RDPSLP resistor sets the output
voltage of the regulator in deeper sleep state.
RDPSLP (Pin 15/Pin 14): Deep Sleep Resistor Pin. Con-
nect a resistor from this pin to V
OA
+
. This resistor sets the
percentage offset of output voltage in deep sleep state.