Datasheet

LTC3735
19
3735fa
APPLICATIONS INFORMATION
After the output voltage enters the ±10% regulation window
centered at V
BOOT
, the internal power good comparator
issues a logic high signal. Refer to the timing diagram in
Figure 7. This signal then enters a logic AND gate, with
MCH_PG being the other input, and the output of the gate
is PG shown in Figure 7. This composite PG signal is then
delayed by t
BOOT
amount of time and then becomes MD.
As soon as MD is asserted, the output voltage changes
from V
BOOT
to V
VID
, a voltage level totally controlled by
the six VID bits. In the LTC3735, the time t
BOOT
is set to
be 15 switching cycles:
t
BOOT
= 15
1
f
S
If f
S
is set at 210kHz, t
BOOT
= 71µs
If f
S
is set at 550kHz, t
BOOT
= 27µs
Output Voltage Set in Deep Sleep and Deeper Sleep
States (Refer to the Functional Diagram)
The output voltage can be offset by the STP_CPUB signal.
When STP_CPUB becomes low, the output voltage will be
a certain percentage lower than that set by the VID bits in
Table 2. This state is defined to be the deep sleep state.
Referring to the Functional Diagram, we can caluculate
the STP_CPUB offset to be:
STP%= –
R3
R3+ R4
•100%
By using different R4 resistors, STP_CPUB offset can be
programmed.
The output voltage could also be set by external resistors
R6 and R4 when DPRSLPVR input is high. This state is
defined to be the deeper sleep state. The output voltage
is set to V
DPRSLPVR
, regardless of the VID setting:
V
DPRSLPVR
= 0.6V •
R2• R3+ R6||R4
( )
R6||R4
( )
• R1+ R2
( )
By using different value R6 resistors, V
DPRSLPVR
can be
programmed.
(The digital input threshold voltage is set to 1.8V for
STP_CPUB, DPRSLPVR and MCH_PG inputs.)
Power Good Masking
The PGOOD output monitors V
OUT
. When V
OUT
is not
within ±10% of the set point, PGOOD is pulled low with
an internal MOSFET. When V
OUT
is within the regulation
window, PGOOD is high impedance. PGOOD should be
pulled up by an external resistor.
During VID changes, deep sleep and deeper sleep transi-
tions, the output voltage can initially be out of the ±10%
window of the newly set regulation point. To avoid nui-
sance indications from PGOOD, a timer masks PGOOD for
110µs. If V
OUT
is still out of regulation after this blanking
time, PGOOD goes low. Any overvoltage or undervoltage
condition is also masked for 110µs before it is reported
by PGOOD.
INTERNAL PG
(OUTPUT OF
INTERNAL
POWER GOOD
COMPARATOR)
MCH_PG
COMPOSITE PG
(=(INTERNAL PG)
AND (MCH_PG))
MD
V
OUT
VID BITS
INVALID
VALID
RUN/SS
1.5V
90% V
BOOT
V
BOOT
V
VID
t
BOOT
TIME
3735 F07
Figure 7. Start-Up Timing Diagram