Datasheet

LTC3734
21
3734fa
APPLICATIONS INFORMATION
output. Efficiency varies as the inverse square of V
OUT
for
the same external components and output power level.
The combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input volt-
ages (typically 12V or greater). Transition losses can be
estimated from:
TransitionLoss = V
IN
2
•
I
OUT
2
• f •C
RSS
•R
DR
•
1
V
DR
– V
TH(MIN)
+
1
V
TH(MIN)






3) PV
CC
drives both top and bottom MOSFETs. The MOSFET
driver current results from switching the gate capacitance
of the power MOSFETs. Each time a MOSFET gate is
switched from low to high to low again, a packet of charge
dQ moves from PV
CC
to ground. The resulting dQ/dt is a
current out of PV
CC
that is typically much larger than the
control circuit current. In continuous mode, I
GATECHG
=
(Q
T
+ Q
B
)f, where Q
T
and Q
B
are the gate charges of the
topside and bottom side MOSFETs and f is the switching
frequency.
4) The input capacitor has the difficult job of filtering the
large RMS input current to the regulator. It must have a
very low ESR to minimize the AC I
2
R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
Other losses, including C
OUT
ESR loss, Schottky diode
conduction loss during dead time, inductor core loss and
internal control circuitry supply current generally account
for less than 2% additional loss.
Checking Transient Response
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to ∆I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I
TH
pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The I
TH
external components shown
in the Figure 1 circuit will provide an adequate starting
point for most applications.
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon first because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of <1µs will
produce output voltage and I
TH
pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step result-
ing from the step change in output current may not be
within
the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why
it is better to look at the I
TH
pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased
by increasing R
C
and the bandwidth of the loop will be
increased by decreasing C
C
. If R
C
is increased by the
same factor that C
C
is decreased, the zero frequency will
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.