Datasheet

LTC3731
27
3731fc
APPLICATIONS INFORMATION
The ripple frequency is also increased by three, fur-
ther reducing the required output capacitance when
V
CC
< 3V
OUT
as illustrated in Figure 6.
The addition of more phases, by phase locking additional
controllers, always results in no net input or output
ripple at V
OUT
/V
IN
ratios equal to the number of stages
implemented. Designing a system with multiple stages
close to the V
OUT
/V
IN
ratio will significantly reduce the
ripple voltage at the input and outputs and thereby improve
efficiency, physical size and heat generation of the overall
switching power supply. Refer to Application Note77 for
more information on PolyPhase circuits.
Efficiency Calculation
To estimate efficiency, the DC loss terms include the
input and output capacitor ESR, each MOSFET R
DS(ON)
,
inductor resistance R
L
, the sense resistance R
SENSE
and
the forward drop of the Schottky rectifier at the operating
output current and temperature. Typical values for the
design example given previously in this data sheet are:
Main MOSFET R
DS(ON)
= 7mΩ (9mΩ at 90°C)
Sync MOSFET R
DS(ON)
= 7mΩ (9mΩ at 90°C)
C
INESR
= 20mΩ
C
OUTESR
= 3mΩ
R
L
= 2.5mΩ
R
SENSE
= 3mΩ
V
SCHOTTKY
= 0.8V at 15A (0.7V at 90°C)
V
OUT
= 1.3V
V
IN
= 12V
I
MAX
= 45A
δ = 0.5%°C (MOSFET temperature coefficient)
N = 3
f = 400kHz
The main MOSFET is on for the duty factor V
OUT
/V
IN
and
the synchronous MOSFET is on for the rest of the period
or simply (1 – V
OUT
/V
IN
). Assuming the ripple current is
small, the AC loss in the inductor can be made small if
a good quality inductor is chosen. The average current,
I
OUT
, is used to simplify the calculations. The equation
below is not exact but should provide a good technique
for the comparison of selected components and give a
result that is within 10% to 20% of the final application.
Determining the MOSFETs
’ die temperature may require
iterative calculations if one is not familiar with typical
performance. A maximum operating junction temperature
of 90° to 100°C for the MOSFETs is recommended for
high reliability applications.
Common output path DC loss:
P
COMPATH
≈N
I
MAX
N






2
R
L
+R
SENSE
( )
+ C
OUTESR
Loss
This totals 3.7W + C
OUTESR
loss.
Total of all three main MOSFETs’ DC loss:
P
MAIN
= N
V
OUT
V
IN






I
MAX
N






2
1+ δ
( )
R
DS(ON)
+ C
INESR
Loss
This totals 0.87W + C
INESR
loss (at 90°C).
Total of all three synchronous MOSFETs’ DC loss:
P
SYNC
= N 1–
V
OUT
V
IN






I
MAX
N






2
1+ δ
( )
R
DS(ON)
This totals 7.2W at 90°C.
Total of all three main MOSFETs’ AC loss:
P
MAIN
≈ 3(V
IN
)
2
45A
(2)(3)
(2Ω)(1000pF)
1
5V – 1.8V
+
1
1.8V






(400kHz)= 6.3W