Datasheet

LTC3731
15
3731fc
APPLICATIONS INFORMATION
Power MOSFET and D1, D2, D3 Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and “on” resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than one-third of the input voltage. In applications
where V
IN
>> V
OUT
, the top MOSFETs’ “on” resistance
is normally less important for overall efficiency than its
input capacitance at operating frequencies above 300kHz.
MOSFET manufacturers have designed special purpose
devices that provide reasonably low “on” resistance with
significantly reduced input capacitance for the main switch
application in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, V
CC
, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV
DSS
specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “on”
resistance R
DS(ON)
, input capacitance, input voltage and
maximum output current.
MOSFET input capacitance is a combination of sev-
eral components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 5).
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V
DS
drain
voltage, but can be adjusted for different V
DS
voltages by
multiplying by the ratio of the application V
DS
to the curve
specified V
DS
values. A way to estimate the C
MILLER
term
is to take the change in gate charge from points a and b
on a manufacturer’s data sheet and divide by the stated
V
DS
voltage specified. C
MILLER
is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C
RSS
and C
OS
are specified sometimes but
definitions of these parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V
OUT
V
IN
Synchronous Switch Duty Cycle =
V
IN
– V
OUT
V
IN






The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
MAIN
=
V
OUT
V
IN
I
MAX
N






2
1+ δ
( )
R
DS(ON)
+
V
IN
2
I
MAX
2N
R
DR
( )
C
MILLER
( )
•
1
V
CC
– V
TH(IL)
+
1
V
TH(IL)








f
( )
P
SYNC
=
V
IN
– V
OUT
V
IN
I
MAX
N






2
1+ δ
( )
R
DS(ON)
+
–
V
DS
V
IN
3731 F05
V
GS
MILLER EFFECT
Q
IN
a b
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
–
Figure 5. Gate Charge Characteristic