Datasheet
26
LTC3727/LTC3727-1
3727fc
2. Are the signal and power grounds kept separate? The
combined LTC3727 signal ground pin and the ground
return of C
INTVCC
must return to the combined C
OUT
(–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the C
IN
capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to the
(–) terminals of the input capacitor by placing the capaci-
tors next to each other and away from the Schottky loop
described above.
3. Do the LTC3727 V
OSENSE
pins resistive dividers con-
nect to the (+) terminals of C
OUT
? The resistive divider
must be connected between the (+) terminal of C
OUT
and
signal ground. The R2 and R4 connections should not be
along the high current input feeds from the input
capacitor(s).
4. Are the SENSE
–
and SENSE
+
leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE
+
and SENSE
–
should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.
5. Is the INTV
CC
decoupling capacitor connected close to
the IC, between
the INTV
CC
and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1μF ceramic capacitor placed immediately
next to the INTV
CC
and PGND pins can help improve noise
performance substantially.
APPLICATIO S I FOR ATIO
WUUU
Figure 10. LTC3727 Recommended Printed Circuit Layout Diagram
C
B2
C
B1
R
PU
PGOOD
V
PULL-UP
(<7V)
C
INTVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
C
IN
D1
M1 M2
M3 M4
D2
+
C
VIN
V
IN
R
IN
INTV
CC
3.3V
R4R3
R2
R1
RUN/SS1
SENSE1
+
SENSE1
–
V
OSENSE1
PLLFLTR
PLLIN
FCB
I
TH1
SGND
3.3V
OUT
I
TH2
V
OSENSE2
SENSE2
–
SENSE2
+
PGOOD
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC3727
L1
L2
C
OUT1
V
OUT1
GND
V
OUT2
3727 F10
+
C
OUT2
+
R
SENSE
R
SENSE
f
IN