Datasheet

LTC3727A-1
20
3727a1fa
A comparator monitors the output for overvoltage
conditions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage. When
this condition is sensed, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if V
OUT
returns to a safe
level, normal operation automatically resumes. A shorted
top MOSFET will result in a high current condition which
will open the system fuse. The switching regulator will
regulate properly with a leaky top MOSFET by altering the
duty cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The LTC3727A-1 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the center
frequency f
O
. A voltage applied to the PLLFLTR pin of 1.2V
corresponds to a frequency of approximately 380kHz. The
nominal operating frequency range of the LTC3727A-1 is
250kHz to 550kHz.
The phase detector used is an edge sensitive digital
type which provides zero degrees phase shift between
the external and internal oscillators. This type of phase
detector will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, Δf
H
, is equal to the capture range, Δf
C
:
Δf
H
= Δf
C
= ±0.5 f
O
(250kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
fi lter network on the PLLFLTR pin.
APPLICATIONS INFORMATION
If the external frequency (f
PLLIN
) is greater than the
oscillator frequency f
OSC
, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency is
less than f
OSC
, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. Thus the voltage on the PLLFLTR pin is
adjusted until the phase and frequency of the external and
internal oscillators are identical. At this stable operating
point the phase comparator output is open and the fi lter
capacitor C
LP
holds the voltage. The LTC3727A-1 PLLIN
pin must be driven from a low impedance source such as
a logic gate located close to the pin. When using multiple
LTC3727A-1s for a phase-locked system, the PLLFLTR pin
of the master oscillator should be biased at a voltage that
will guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A DC voltage of 0.7V to 1.7V applied
to the master oscillator’s PLLFLTR pin is recommended
in order to meet this requirement. The resultant operating
frequency can range from 310kHz to 470kHz.
The loop fi lter components (C
LP
, R
LP
) smooth out the cur-
rent pulses from the phase detector and provide a stable
input to the voltage controlled oscillator. The fi lter com-
ponents C
LP
and R
LP
determine how fast the loop acquires
lock. Typically R
LP
=10kΩ and C
LP
is 0.01μF to 0.1μF.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest time duration
that the LTC3727A-1 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
t
V
Vf
ON MIN
OUT
IN
()
()
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