Datasheet

LTC3721-1
6
sn37211 37211fs
V
REF
(Pin 1/Pin 15): Output of the 5.0V Reference. V
REF
is
capable of supplying up to 18mA to external circuitry. V
REF
should be decoupled to GND with a 1µF ceramic capacitor.
DRVB (Pin 4/Pin 1): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
V
CC
(Pin 5/Pin 2): Supply Voltage Input to the LTC3721-1
and 10.25V Shunt Regulator. The chip is enabled after V
CC
has risen high enough to allow the V
CC
shunt regulator to
conduct current and the UVLO comparator threshold is
exceeded. Once the V
CC
shunt regulator has turned on,
V
CC
can drop to as low as 6V (typical) and maintain
operation. Bypass V
CC
to GND with a high quality 1µF or
larger ceramic capacitor to supply the transient currents
caused by the high speed switching and capacitive loads
presented by the on chip totem pole drivers.
DRVA (Pin 6/Pin 3): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
GND (Pin 7/Pin 4, Pin 5, Pin 17): All circuits in the
LTC3721-1 are referenced to GND. Use of a ground plane
is highly recommended. V
IN
and V
REF
bypass capacitors
must be terminated with a star configuration as close to
DESCRIPTIO S
U
PI
U
GND as practical for best performance. For the 4mm ×
4mm QFN package only, the internal power (PGND) and
signal (SGND) buses are connected separately to pins 4
and 5 respectively, and the exposed pad must be soldered
to PCB ground.
C
T
(Pin 8/Pin 6): Timing Capacitor for the Oscillator. Use
a ±5% or better low ESR ceramic capacitor for best
results. C
T
ramp amplitude is 2.35V peak-to-peak
(typical).
DPRG (Pin 9/Pin 8): Programming Input for Push-Pull
Dead-Time. Connect a resistor between DPRG and V
REF
to
program the dead-time. The nominal voltage on DPRG is
2V.
CS (Pin 10/Pin 9): Input to Pulse-by-Pulse and Overload
Current Limit Comparators, Output of Slope Compensa-
tion Circuitry. The pulse-by-pulse comparator has a nomi-
nal 300mV threshold, while the overload comparator has
a nominal 600mV threshold. An internal switch discharges
CS to GND after every timing period. Slope compensation
current flows out of CS during the PWM period.
An external resistor connected from CS to the external
current sense resistor programs the amount of slope
compensation.
COMP (Pin 11/Pin 10): Error Amplifier Output, Inverting
Input to Phase Modulator.
R
LEB
(Pin 12/Pin 11): Timing Resistor for Leading Edge
Blanking. Use a 10k to 100k resistor connected between
R
LEB
and GND to program from 40ns to 310ns of leading
edge blanking of the current sense signal on CS for the
LTC3721-1. A ±1% tolerance resistor is recommended.
The nominal voltage on R
LEB
is 2V. If leading edge blank-
ing is not required, tie R
LEB
to V
REF
to disable.
(GN Package/UF Package)