Datasheet

14
LTC3717
sn3717 3717fs
efficiency source, such as an output derived boost net-
work or alternate supply if available.
4. C
IN
loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I
2
R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C
OUT
ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
If you make a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ∆I
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components shown in Figure 6
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: V
IN
= V
REF
= 2.5V, V
EXTVCC
= 5V, V
OUT
=
1.25V ±5%, I
OUT(MAX)
= 10A, f = 250kHz. First, calculate
the timing resistor with V
ON
= V
OUT
:
R
VV V
V kHz pF V
k
ON
==Ω
125 25 07
0 7 250 10 2 5
514
.(.–.)
( . )( )( ) .
and choose the inductor for about 40% ripple current at
the maximum V
IN
:
APPLICATIO S I FOR ATIO
WUUU
L
V
kHz A
V
V
H=−






=µ
125
250 0 4 10
1
125
25
063
.
( )( . )( )
.
.
.
Selecting a standard value of 0.68µH results in a maximum
ripple current of:
∆=
µ






=I
V
kHz H
V
V
A
L
125
250 0 68
1
125
25
37
.
()(.)
–
.
.
.
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (R
DS(ON)
= 0.0083Ω (NOM) 0.010Ω (MAX),
θ
JA
= 40°C/W) yields a nominal sense voltage of:
V
SNS(NOM)
= (10A)(1.3)(0.0083Ω) = 108mV
Tying V
RNG
to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 143mV. To check if the current limit is acceptable,
assume a junction temperature of about 40°C above a
70°C ambient with ρ
110°C
= 1.4:
I
mV
AA
LIMIT
≥
Ω
+=
143
14 0010
1
2
3 7 12 1
(.)(. )
(. ) .
and double check the assumed T
J
in the MOSFET:
P
VV
V
AW
BOT
=Ω=
25 125
25
12 1 1 4 0 010 1 02
2
.–.
.
(.)(.)(. ) .
T
J
= 70°C + (1.02W)(40°C/W) = 111°C
Because the top MOSFET is on roughly the same amount
of time as the bottom MOSFET, the same Si4874 can be
used as the synchronous MOSFET.
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C
IN
is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013Ω to minimize output voltage changes due to induc-
tor ripple current and load steps. For current sinking
applications where current flows back to the input through
the top transistor, output capacitors with a similar amount
of bulk C and ESR should be placed on the input as well.