Datasheet

LTC3714
22
3714f
applicaTions inForMaTion
Because the top MOSFET is on for such a short time, a
single IRF7811 will be sufficient. Checking its power dis-
sipation at current limit with ρ
80°C
= 1.2:
P
TOP
=
1.15V
24V
20A
( )
2
1.2
( )
0.013Ω
( )
+
1.7
( )
24V
( )
2
20A
( )
60pF
( )
300kHz
( )
=
0.299W
+
0.353W
=
0.652W
T
J
= 50°C + (0.652W)(50°C/W) = 82.6°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C
IN
is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
ESR of 0.005Ω to minimize output voltage changes due
to inductor ripple current and load steps. The ripple volt-
age will be only:
∆V
OUT(RIPPLE)
= ∆I
L(MAX)
(ESR) = (5.4A) (0.005Ω)
= 27mV
However, a 0A to 15A load step will cause an output
change of up to:
∆V
OUT(STEP)
= ∆I
LOAD
(ESR) = (15A)(0.005Ω) = ±75mV
The complete circuit is shown in Figure 8.
Active Voltage Positioning
Active voltage positioning (also termed load “deregula-
tion” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage at or above the regulation point at zero load, and
below the regulation point at full load, one can use more
of the error budget for the load step. This allows one to
reduce the number of output capacitors by relaxing the
ESR requirement.
In the design example, Figure 8, five 0.025Ω capacitors
are required in parallel to keep the output voltage within
tolerance. Using active voltage positioning, the same
specification can be met with only three capacitors. In this
case, the load step will cause an output voltage change of:
ΔV
OUT(STEP)
= 15A
( )
1
3
⎛
⎝
⎜
⎞
⎠
⎟
0.025Ω
( )
= 125mV
By positioning the output voltage 60mV above the regula-
tion point at no load, it will drop 65mV below the regulation
point after the load step. However, when the load disap-
pears or the output is stepped from 15A to 0A, the 65mV
is recovered. This way, a total of 65mV change is observed
on V
OUT
in all conditions, whereas a total of ±75mV or
150mV is seen on V
OUT
without voltage positioning.
Implementing active voltage positioning requires setting
a precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resistance,
it is prudent to use a sense resistor with active voltage
positioning. In order to minimize power lost in this resis-
tor, a low value of 0.003Ω is chosen. The nominal sense
voltage will now be:
V
SNS(NOM)
= (0.003Ω)(15A) = 45mV
To maintain a reasonable current limit, the voltage on the
V
RNG
pin is reduced to 0.5V by connecting it between
INTV
CC
and GND, corresponding to a 50mV nominal
sense voltage.
Next, the gain of the LTC3714 error amplifier must be
determined. The change in I
TH
voltage for a corresponding
change in the output current is:
ΔI
TH
=
12V
V
RNG
⎛
⎝
⎜
⎞
⎠
⎟
R
SENSE
ΔI
OUT
= 24
( )
0.003Ω
( )
15A
( )
= 1.08V
The corresponding change in the output voltage is deter-
mined by the gain of the error amplifier and feedback divider.
The LTC3714 error amplifier has a transconductance g
m
that is constant over both temperature and a wide ±40mV
input range. Thus, by connecting a load resistance R
VP
to
the I
TH
pin, the error amplifier gain can be precisely set
for accurate voltage positioning.
ΔI
TH
= g
m
R
VP
0.6V
V
OUT
⎛
⎝
⎜
⎞
⎠
⎟
ΔV
OUT