Datasheet

LTC3707-SYNC
23
3707sfa
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from INTV
CC
to ground. The resulting dQ/dt is a current out of INTV
CC
that is typically much larger than the control circuit current.
In continuous mode, I
GATECHG
=f(Q
T
+Q
B
), where Q
T
and
Q
B
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTV
CC
power through the EXTV
CC
switch
input from an output-derived source will scale the V
IN
current required for the driver and control circuits by
a factor of (Duty Cycle)/(Effi ciency). For example, in a
20V to 5V application, 10mA of INTV
CC
current results
in approximately 2.5mA of V
IN
current. This reduces the
mid-current loss from 10% or more (if the driver was
powered directly from V
IN
) to only a few percent.
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous
mode the average output current fl ows through L and
R
SENSE
, but is “chopped” between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same R
DS(ON)
, then the resistance of
one MOSFET can simply be summed with the resistances
of L, R
SENSE
and ESR to obtain I
2
R losses. For example, if
each R
DS(ON)
= 30mΩ, RL = 50mΩ, R
SENSE
= 10mΩ and
R
ESR
= 40mΩ (sum of both input and output capacitance
losses), then the total resistance is 130mΩ. This results
in losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Effi ciency varies as the inverse
square of V
OUT
for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become signifi cant only when operating at high input
APPLICATIONS INFORMATION
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss V I R C
V
IN O MAX D R MILLER
INT
=
1
2
1
2
()
VVCC TH TH
VV
f
+
()
1
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% effi ciency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
C
IN
has adequate charge storage and very low ESR at the
switching frequency. A 25W supply will typically require
a minimum of 20μF to 40μF of capacitance having a
maximum of 20mΩ to 50mΩ of ESR. The LTC3707-SYNC
2-phase architecture typically halves this input capacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by
an amount equal to ΔI
LOAD
(ESR), where ESR is the
effective series resistance of C
OUT
. ΔI
LOAD
also begins to
charge or discharge C
OUT
generating the feedback error
signal that forces the regulator to adapt to the current
change and return V
OUT
to its steady-state value. During
this recovery time V
OUT
can be monitored for excessive
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the I
TH
pin
not only allows optimization of control loop behavior but
also provides a DC coupled and AC fi ltered closed loop
response test point. The DC step, rise time and settling