Datasheet

LTC3707-SYNC
14
3707sfa
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High effi ciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mμ
®
cores. Actual core loss is independent of core
size for a fi xed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mμ. Toroids are very space effi cient,
especially when you can use several layers of wire. Because
they generally lack a bobbin, mounting is more diffi cult.
However, designs for surface mount are available that do
not increase the height signifi cantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for each
controller in the IC: One N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak drive levels are set by the INTV
CC
voltage.
This voltage is typically 5V during start-up (see EXTV
CC
Pin Connection). Consequently, logic-level threshold
MOSFETs must be used in most applications. The only
APPLICATIONS INFORMATION
exception is if low input voltage is expected (V
IN
< 5V);
then, sub-logic level threshold MOSFETs (V
GS(TH)
< 3V)
should be used. Pay close attention to the BV
DSS
speci-
fi cation for the MOSFETs as well; most of the logic level
MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
DS(ON)
, reverse transfer capacitance C
RSS
,
input voltage and maximum output current. When the IC
is operating in continuous mode the duty cycles for the
top and bottom MOSFETs are given by:
Main Switch Duty Cycle
V
V
OUT
IN
=
Synchronous SwitchDuty Cycle
VV
V
IN OUT
IN
=
–
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
V
V
IR
VI
MAIN
OUT
IN
MAX DS ON
IN M
=
()
+
()
+
()
2
2
1
1
2
δ
()
AAX DR MILLER
INTVCC TH TH
RC
VVV
f
()()( )
+
⎡
⎣
⎢
⎤
⎦
⎥
11
–
(()
P
VV
V
IR
SYNC
IN OUT
IN
MAX DS ON
=
()
+
()
–
()
2
1 δ
where δ is the temperature dependency of R
DS(ON)
, R
DR
is
the effective top driver resistance over the (of approximately
4Ω at V
GS
= V
MILLER
), V
IN
is the drain potential and the
change in drain potential in the particular application. V
TH
is the data sheet specifi ed typical gate threshold voltage
specifi ed in the power MOSFET data sheet. C
MILLER
is the
calculated capacitance using the gate charge curve from
the MOSFET data sheet. C
MILLER
is determined by dividing
the increase in charge indicated on the x axis during the
fl at, Miller portion of the curve by the stated V
DS
transition
voltage specifi ed on the curve.