Datasheet

LTC3677-3
36
36773f
operaTion
PUSHBUTTON INTERFACE OPERATION
State Diagram/Operation
Figure 13 shows the LTC3677-3 pushbutton state diagram.
Upon first application of power (V
BUS
, WALL or BAT) an
internal power-on reset (POR) signal places the pushbut-
ton circuitry into the power-off (POFF) state. The following
events cause the state machine to transition out of POFF
into the power-up (PUP) state:
1) ON input LOW for 50ms (PB50MS)
2) PWR_ON input going HIGH (PWR_ON)
Upon entering the PUP state, the pushbutton circuitry
will sequence up LDO2, Buck1 and Buck2 in that order.
One second after entering the PUP state, the pushbutton
circuitry will transition into the power-on (PON) state. Note
that the PWR_ON input must be brought HIGH before
entering the PON state if the part is to remain in the PON
state. Buck3 can be enabled through the EN3 input once
the pushbutton is in the PUP or PON states.
PWR_ON going LOW, or V
OUT
dropping to its undervoltage
lockout (V
OUT
UVLO) threshold will cause the state machine
to leave the PON state and enter the power-down (PDN)
state. The PDN state resets the I
2
C registers as well as
disables Buck1, Buck2 and LDO2 together. Buck3 is also
disabled in the PDN and POFF states. The one second delay
before leaving the power-down state allows the supplies to
power down completely before they can be re-enabled.
PBSTAT Operation
PBSTAT goes LOW 50ms after the initial pushbutton ap-
plication (ON LOW) and will stay low for 50ms minimum.
PBSTAT will go HIGH coincident with ON going HIGH unless
ON goes HIGH before the 50ms minimum LOW time.
Hard Reset and PGOOD Operation
The hard reset event is generated by pressing and holding
the pushbutton (ON input LOW) for 14 seconds. For a
valid hard reset event to occur the initial pushbutton ap-
plication must start in the PUP or PON state. This avoids
causing a hard reset from occurring if the user hangs on
the pushbutton during initial power-up. If a valid hard
reset event is present then the PGOOD output will transi-
tion LOW for about 1.8ms to allow the microprocessor to
reset. The hard reset event does not affect the operating
state or regulator operation.
The PGOOD pin is an open-drain output used to indicate
that Buck1, Buck2 and LDO1 are enabled and have reached
their final regulation voltage. A 230ms delay is included
from the time Buck1, Buck2 and LDO1 reach 92% of their
regulation value to allow a system controller ample time to
reset itself. PGOOD is an open-drain output and requires a
pull-up resistor to an appropriate power source. Optimally
the pull-up resistor is connected to the output of Buck1,
Buck2 or LDO2 so that power is not dissipated while the
regulators are disabled.
Pushbutton Operation and V
OUT
UVLO
As stated earlier V
OUT
dropping to its UVLO threshold
will cause the pushbutton to leave the power-on state and
enter the power-down state, thus powering down Buck1,
Buck2, Buck3 and LDO2. Additionally, LDO1 is disabled
when in UVLO. Thus, all LTC3677-3 supplies are disabled
and remain disabled as long as the V
OUT
UVLO condition
exists. It is not possible to power up any of the LTC3677-3
generated supplies while V
OUT
is below the V
OUT
UVLO
threshold.
Figure 12. Pushbutton State Diagram
1SEC
POR
35773 F13
1SEC
PB50ms +
PWR_ON
PUP
PONPOFF
PDN
UVLO +
PWR_ON