Datasheet

LTC3677-3
34
36773f
operaTion
I
2
C Bus Write Operation
The master initiates communication with the LTC3677-3
with a START condition and the LTC3677-3’s write address.
If the address matches that of the LTC3677-3, the LTC3677-3
returns an acknowledge. The master should then deliver
the sub-address. Again the LTC3677-3 acknowledges and
the cycle is repeated for the data byte. The data byte is
transferred to an internal holding latch upon the return of
its acknowledge by the LTC3677-3. This procedure must be
repeated for each sub-address that requires new data. After
one or more cycles of [ADDRESS][SUB-ADDRESS][DATA],
the master may terminate the communication with a STOP
condition. Alternatively, a REPEAT-START condition can
be initiated by the master and another chip on the I
2
C bus
can be addressed. This cycle can continue indefinitely
and the LTC3677-3 will remember the last input of valid
data that it received. Once all chips on the bus have been
addressed and sent valid data, a global STOP can be sent
and the LTC3677-3 will update its command latches with
the data that it received.
I
2
C Bus Read Operation
The bus master reads the status of the LTC3677-3 with
a START condition followed by the LTC3677-3 read ad-
dress. If the read address matches that of the LTC3677-3,
the LTC3677-3 returns an acknowledge. Following the
acknowledgement of their read address, the LTC3677-3
returns one bit of status information for each of the next
8 clock cycles. A STOP command is not required for the
bus read operation.
I
2
C Input Data
There is one byte of data that can be written to on the
LTC3677-3. The byte is accessed through the sub-address
0x00. At first power application (V
BUS
, WALL or BAT)
all bits default to 0. Additionally, all bits are cleared to 0
when DV
CC
drops below its undervoltage lock out or if the
pushbutton enters the power down (PDN) state.
Table 5 shows the byte of data that can be written to at
sub-address 0x00. This byte of data is referred to as the
buck control register.
Table 5. Buck Control Register
BUCK CONTROL
REGISTER
ADDRESS: 00010010
SUB-ADDRESS: 00000000
BIT NAME FUNCTION
B0 N/A Not Used—No Effect On Operation
B1 N/A Not Used—No Effect On Operation
B2 BK1BRST Buck1 Burst Mode Enable
B3 BK2BRST Buck2 Burst Mode Enable
B4 BK3BRST Buck2 Burst Mode Enable
B5 SLEWCTL1 Buck SW Slew Rate: 00 = 1ns,
01 = 2ns, 10 = 4ns, 11 = 8ns
B6 SLEWCTL2
B7 N/A Not Used—No Effect On Operation
Bits B2, B3, and B4 set the operating modes of the step-
down switching regulators (bucks). Writing a 1 to any of
these three registers will put that respective buck converter
in the high efficiency Burst Mode operation, while a 0 will
enable the low noise pulse-skipping mode of operation.
The B5 and B6 bits adjust the slew rate of all SW pins
together so they all slew at the same rate. It is recom-
mended that the fastest slew rate (B6:B5 = 00) be used
unless EMI is an issue in the application as slower slew
rates cause reduced efficiency.
I
2
C Output Data
One status byte may be read from the LTC3677-3, as
shown in Table 6. A 1 read back in the any of the bit posi-