Datasheet

LTC3677-3
33
36773f
operaTion
I
2
C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3677-3 is written
to (write address), it acknowledges its write address as
well as the subsequent two data bytes. When read from
(read address), the LTC3677-3 acknowledges its read ad-
dress only. The bus master should acknowledge receipt
of information from the LTC3677-3.
An acknowledge (active LOW) generated by the LTC3677-3
lets the master know that the latest byte of information was
received. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH)
during the acknowledge clock cycle. The LTC3677-3 pulls
down the SDA line during the write acknowledge clock
pulse so that it is a stable LOW during the HIGH period
of this clock pulse.
When the LTC3677-3 is read from, it releases the SDA line
so that the master may acknowledge receipt of the data.
Since the LTC3677-3 only transmits one byte of data, a
master not acknowledging the data sent by the LTC3677-3
has no I
2
C specific consequence on the operation of the
I
2
C port.
I
2
C Slave Address
The LTC3677-3 responds to a 7-bit address which has
been factory programmed to b’0001001[R/W]’. The LSB
of the address byte, known as the read/write bit, should be
0 when writing data to the LTC3677-3 and 1 when reading
data from it. Considering the address an 8-bit word, then
the write address is 0x12 and the read address is 0x13.
The LTC3677-3 will acknowledge both its read and write
address.
I
2
C Sub-Addressed Writing
The LTC3677-3 has one command register for control
input. It is accessed by the I
2
C port via a sub-addressed
writing system.
Each write cycle of the LTC3677-3 consists of exactly
three bytes. The first byte is always the LTC3677-3’s write
address. The second byte represents the LTC3677-3’s
sub-address. The sub-address is a pointer which directs
the subsequent data byte within the LTC3677-3. The third
byte consists of the data to be written to the location
pointed to by the sub-address. The LTC3677-3 contains
control registers at only sub-address location 0x00. Sub-
addresses outside 0x00 should not be written to as they
access functionality not available in the LTC3677-3.
t
SU, DAT
t
HD, STA
t
HD, DAT
SDA
SCL
t
SU, STA
t
HD, STA
t
SU, STO
36773 F11
t
BUF
t
LOW
t
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
t
SP
ACK ACK
1 2 3
ADDRESS WR
4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
0 0 0 1 0 0 1 0
0 0 0 1 0 0 1 0
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
ACK
STOPSTART
SDA
SCL
DATA BYTE A DATA BYTE B
Figure 11. I
2
C Timing Diagram