Datasheet

LTC3677-3
32
36773f
operaTion
choice of which style inductor to use often depends more
on the price versus size, performance, and any radiated
EMI requirements than on what the step-down switching
regulators requires to operate. The inductor value also has
an effect on Burst Mode operation. Lower inductor values
will cause Burst Mode switching frequency to increase.
Table 3 shows several inductors that work well with the
step-down switching regulators. These inductors offer a
good compromise in current rating, DCR and physical
size. Consult each manufacturer for detailed information
on their entire selection of inductors.
Input/Output Capacitor Selection
Low ESR (equivalent series resistance) ceramic capacitors
should be used at both step-down switching regulator
outputs as well as at each step-down switching regulator
input supply. Only X5R or X7R ceramic capacitors should
be used because they retain their capacitance over wider
voltage and temperature ranges than other ceramic types.
A 10μF output capacitor is sufficient for the step-down
switching regulator outputs. For good transient response
and stability the output capacitor for step-down switching
regulators should retain at least 4μF of capacitance over
operating temperature and bias voltage. Each switching
regulator input supply should be bypassed with a 2.2μF
capacitor. Consult with capacitor manufacturers for de-
tailed information on their selection and specifications
of ceramic capacitors. Many manufacturers now offer
very thin (<1mm tall) ceramic capacitors ideal for use in
height-restricted designs. Table 4 shows a list of several
ceramic capacitor manufacturers.
Table 4. Ceramic Capacitor Manufacturers
AVX www.avxcorp.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
Vishay Siliconix www.vishay.com
TDK www.tdk.com
I
2
C OPERATION
I
2
C Interface
The LTC3677-3 may communicate with a bus master us-
ing the standard I
2
C 2-wire interface. The timing diagram
in Figure 11 shows the relationship of the signals on the
bus. The two bus lines, SDA and SCL, must be HIGH
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines. The LTC3677-3 is both a slave
receiver and slave transmitter. The I
2
C control signals,
SDA and SCL are scaled internally to the DV
CC
supply.
DV
CC
should be connected to the same power supply as
the bus pull-up resistors.
The I
2
C port has an undervoltage lockout on the DV
CC
pin.
When DV
CC
is below approximately 1V, the I
2
C serial port
is cleared and registers are set to the default configura-
tion of all zeros.
I
2
C Bus Speed
The I
2
C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I
2
C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
I
2
C START and STOP Conditions
A bus master signals the beginning of communications by
transmitting a START condition. A START condition is gen-
erated by transitioning SDA from HIGH to LOW while SCL is
HIGH. The master may transmit either the slave write or the
slave read address. Once data is written to the LTC3677-3,
the master may transmit a STOP condition which com-
mands the LTC3677-3 to act upon its new command set. A
STOP condition is sent by the master by transitioning SDA
from LOW to HIGH while SCL is HIGH. The bus is then free
for communication with another I
2
C device.
I
2
C Byte Format
Each byte sent to or received from the LTC3677-3 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3677-3
most significant bit (MSB) first.