Datasheet

LTC3677-3
17
36773f
pin FuncTions
NTC (Pin 35): The NTC pin connects to a battery’s therm-
istor to determine if the battery is too hot or too cold
to charge. If the battery’s temperature is out of range,
charging is paused until it drops back into range. A low
drift bias resistor is required from NTCBIAS to NTC and
a thermistor is required from NTC to ground.
PROG (Pin 36): Charge Current Program and Charge
Current Monitor Pin. Connecting a resistor from PROG
to ground programs the charge current:
I
V
R
A
CHG
PROG
=
( )
1000

If sufficient input power is available in constant-current
mode, this pin servos to 1V. The voltage on this pin always
represents the actual charge current.
IDGATE (Pin 37): Ideal Diode Gate Connection. This
pin controls the gate of an optional external P-channel
MOSFET transistor used to supplement the internal ideal
diode. The source of the P-channel MOSFET should be
connected to V
OUT
and the drain should be connected to
BAT. It is important to maintain high impedance on this
pin and minimize all leakage paths.
BAT (Pin 38): Single-Cell Li-Ion Battery Pin. Depending
on available power and load, a Li-Ion battery on BAT will
either deliver system power to V
OUT
through the ideal
diode or be charged from the battery charger.
V
OUT
(Pin 39): Output Voltage of the PowerPath Controller
and Input Voltage of the Battery Charger. The majority of
the portable product should be powered from V
OUT
. The
LTC3677-3 will partition the available power between the
external load on V
OUT
and the internal battery charger.
Priority is given to the external load and any extra power
is used to charge the battery. An ideal diode from BAT
to V
OUT
ensures that V
OUT
is powered even if the load
exceeds the allotted input current from V
BUS
or if the V
BUS
power source is removed. V
OUT
should be bypassed with
a low impedance multilayer ceramic capacitor.
V
BUS
(Pin 40): USB Input Voltage. V
BUS
will usually be
connected to the USB port of a computer or a DC output
wall adapter. V
BUS
should be bypassed with a low imped-
ance multilayer ceramic capacitor.
ACPR (Pin 41): Wall Adapter Present Output (Active Low).
A low on this pin indicates that the wall adapter input com-
parator has had its input pulled above its input threshold
(typically 4.3V). This pin can be used to drive the gate of
an external P-channel MOSFET to provide power to V
OUT
from a power source other than a USB port.
EXTPWR (Pin 42): External Power Present Output (Active
Low, Open-Drain Output). A low on this pin indicates that
external power is present at either the V
BUS
or WALL input.
For EXTPWR to signal V
BUS
present, V
BUS
must exceed
the V
BUS
undervoltage lockout threshold. For EXTPWR to
signal WALL present, WALL must exceed the absolute and
differential WALL input thresholds. The EXTPWR signal is
independent of the I
LIM1
and I
LIM0
pins. Thus, it is possible
to have the input current limit circuitry in suspend with
EXTPWR showing a valid charging level on V
BUS
.
CLPROG (Pin 43): Input Current Program and Input
Current Monitor Pin. A resistor from CLPROG to ground
determines the upper limit of the current drawn from the
V
BUS
pin (i.e., the input current limit). A precise fraction
of the input current, h
CLPROG
, is sent to the CLPROG pin.
The input PowerPath delivers current until the CLPROG
pin reaches 2V (10x mode), 1V (5x mode) or 0.2V (1x
mode). Therefore, the current drawn from V
BUS
will be
limited to an amount given by h
CLPROG
and R
CLPROG
. In
USB applications the resistor R
CLPROG
should be set to
no less than 2.1k.
CHRG (Pin 44): Open-Drain Charge Status Output. The
CHRG pin indicates the status of the battery charger. If
CHRG is high then the charger is near the float voltage
(charge current less than 1/10th programmed charge cur-
rent) or charging is complete and charger is disabled. A low
on CHRG indicates that the charger is enabled. For more
information see the Charge Status Indication section.
GND (Exposed Pad Pin 45): The exposed package pad is
ground and must be soldered to PCB ground for electrical
contact and rated thermal performance.