Datasheet

LTC3677-3
16
36773f
pin FuncTions
N-channel MOSFET pass transistor. When the voltage on
this pin exceeds a preset level, the OVGATE pin will be
pulled to GND to disable the pass transistor and protect
downstream circuitry.
DV
CC
(Pin 10): Supply Voltage for I
2
C Lines. This pin sets
the logic reference level of the LTC3677-3. A UVLO circuit
on the DV
CC
pin forces all registers to all 0s whenever DV
CC
is <1V. Bypass to GND with a 0.1µF capacitor.
SDA (Pin 11): I
2
C Data Input. Serial data is shifted one
bit per clock to control the LTC3677-3. The logic level for
SDA is referenced to DV
CC
.
SCL (Pin 12): I
2
C Clock Input. The logic level for SCL is
referenced to DV
CC
.
OVGATE (Pin 13): Overvoltage Protection Gate Output.
Connect OVGATE to the gate pin of an external N-channel
MOSFET pass transistor. The source of the transistor should
be connected to V
BUS
and the drain should be connected
to the product’s DC input connector. In the absence of an
overvoltage condition, this pin is connected to an internal
charge pump capable of creating sufficient overdrive to
fully enhance this transistor. If an overvoltage condition
is detected, OVGATE is brought rapidly to GND to prevent
damage. OVGATE works in conjunction with OVSENSE to
provide this protection.
PWR_ON (Pin 14): Logic Input Used to Keep Buck1, Buck2
and LDO2 Enabled After Power-Up. May also be used to
enable regulators directly (sequence = LDO2 → Buck1 →
Buck2). See the Pushbutton Interface Operation section
for more information.
ON (Pin 15): Pushbutton Input. A weak internal pull-up
forces ON high when left floating. A normally open push-
button is connected from ON to ground to force a low
state on this pin.
PBSTAT (Pin 16): Open-drain output is a debounced
and buffered version of ON to be used for processor
interrupts.
EN3 (Pin 17): Enable Pin for Step-Down Switching
Regulator 3 (Buck3) .
PGOOD (Pin 21): Open-Drain Output. PGOOD indicates that
Buck1, Buck2 and LDO1 are within 8% of final regulation
value. There is a 230ms delay from all regulators reaching
regulation and PGOOD going high.
LDO1_FB (Pin 23): Feedback Voltage Input for Low Drop-
out Linear Regulator 1 (LDO1). LDO1 output voltage is
set using an external resistor divider between LDO1 and
LDO1_FB.
LDO2_FB (Pin 24): Feedback Voltage Input for Low Drop-
out Linear Regulator 2 (LDO2). LDO2 output voltage is
set using an external resistor divider between LDO2 and
LDO2_FB.
FB2 (Pin 25): Feedback Input for Step-Down Switching
Regulator 2 (Buck2). This pin servos to a fixed voltage of
0.8V when the control loop is complete.
FB1 (Pin 26): Feedback Input for Step-Down Switching
Regulator 1 (Buck1). This pin servos to a fixed voltage of
0.8V when the control loop is complete.
V
INLDO1
(Pin 27): Input Supply of Low Dropout Linear
Regulator 1 (LDO1). This pin should be bypassed to ground
with a 1µF or greater ceramic capacitor.
LDO1 (Pin 28): Output of Low Dropout Linear Regulator 1.
LDO1 is an always-on LDO and will be enabled whenever
the part is not in V
OUT
UVLO. This pin must be bypassed
to ground with a 1µF or greater ceramic capacitor.
LDO2 (Pin 29): Output of Low Dropout Linear Regulator 2.
This pin must be bypassed to ground with a 1µF or greater
ceramic capacitor.
V
INLDO2
(Pin 30): Input Supply of Low Dropout Linear
Regulator 2 (LDO2). This pin should be bypassed to ground
with a 1µF or greater ceramic capacitor.
SW2 (Pin 31): Power Transmission (Switch) Pin for Step-
Down Switching Regulator 2 (Buck2).
V
IN12
(Pin 32): Power Input for Step-Down Switching
Regulators 1 and 2. This pin will generally be connected
to V
OUT
.
SW1 (Pin 33): Power Transmission (Switch) Pin for Step-
Down Switching Regulator 1 (Buck1).
NTCBIAS (Pin 34): Output Bias Voltage for NTC. A
resistor from this pin to the NTC pin will bias the NTC
thermistor.