LTC3677-3 Highly Integrated Portable Product PMIC Description Features n n n n n n n n n n n Full Featured Li-Ion/Polymer Charger/PowerPath™ Controller with Instant-On Operation Triple Adjustable High Efficiency Step-Down Switching Regulators (800mA, 500mA, 500mA IOUT) I2C Adjustable SW Slew Rates for EMI Reduction High Temperature Battery Voltage Reduction Improves Safety and Reliability Overvoltage Protection Controller for USB (VBUS)/Wall Inputs Provide Protection to 30V 1.
LTC3677-3 Table of Contents Features............................................................................................................................. 1 Applications........................................................................................................................ 1 Typical Application................................................................................................................ 1 Description...................................................................
LTC3677-3 Pin Configuration VBUS, VOUT , VIN12, VIN3, VINLDO1, VINLDO2, WALL t < 1ms and Duty Cycle < 1%.................... –0.3V to 7V Steady State............................................. –0.3V to 6V CHRG, BAT, PWR_ON, EXTPWR, PBSTAT, PGOOD, FB1, FB2, FB3, LDO1, LDO1_FB, LDO2, LDO2_FB, DVCC, SCL, SDA, EN3.................. –0.3V to 6V NTC, PROG, CLPROG, ON, ILIM0, ILIM1 (Note 4)............................................ –0.3V to VCC + 0.3V IVBUS, IVOUT , IBAT, Continuous (Note 16).................
LTC3677-3 Electrical Characteristics Power Manager. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = 5V, WALL = 0V, VINLDO2 = VINLOD1 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Power Supply VBUS Input Supply Voltage 4.
LTC3677-3 Electrical Characteristics Power Manager. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = 5V, WALL = 0V, VINLDO2 = VINLOD1 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted.
LTC3677-3 Electrical Characteristics I2C Interface. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. DVCC = 3.3V, VOUT = 3.8V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP DVCC Input Supply Voltage IDVCC DVCC Supply Current VDVCC,UVLO DVCC UVLO 1.0 VIH Input High Voltage 50 VIL Input Low Voltage IIH Input High Leakage Current SDA = SCL = DVCC = 5.
LTC3677-3 Electrical Characteristics Step-Down Switching Regulators. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VOUT = VIN12 = VIN3 = 3.8V, all regulators enabled unless otherwise noted.
LTC3677-3 Electrical Characteristics LDO Regulators. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VINLDO1 = VINLDO2 = VOUT = 3.8V, LDO1 and LDO2 enabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LDO Regulator 1 (LDO1-Always On) VINLDO1 Input Voltage Range VINLDO1 ≤ VOUT + 0.
LTC3677-3 Electrical Characteristics Pushbutton Controller. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VOUT = 3.8V, unless otherwise noted.
LTC3677-3 Electrical Characteristics Note 4: VCC is the greater of VBUS, VOUT or BAT. Note 5: Total input current is the sum of quiescent current, IBUSQ, and measured current given by VCLPROG/RCLPROG • (hCLPROG + 1). Note 6: hC/10 is expressed as a fraction of measured full charge current with indicated PROG resistor. Note 7: The current limit features of this part are intended to protect the IC from short term or intermittent fault conditions.
LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified 10x MODE 240 700 220 600 RON (mΩ) IVBUS (mA) 800 5x MODE 500 120 1x MODE 100 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 0 –50 125 6 4.24 5 4.22 4 300 3 200 SAFETY TIMER 2 TERMINATION C/10 IBAT 5 6 0 4.10 4.18 0 200 400 600 IBAT (mA) 2.8 4.04 –50 –25 1000 800 3.2 3.6 VBAT (V) VBAT = 3.2V 36773 G10 0 125 36773 G09 30 VBAT = 3.6V VBAT = 4.2V VFWD (V) 4.4 100 VBAT = 3.
LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified Input Disconnect Waveform Input Connect Waveform Switching from 1x to 5x Mode VBUS 5V/DIV VBUS 5V/DIV VOUT 5V/DIV VOUT 5V/DIV IBUS 0.5A/DIV IBUS 0.5A/DIV IBUS 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k 36773 G13 1ms/DIV ILIM0/ILIM1 5V/DIV VBAT = 3.
LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified EFFICIENCY (%) 80 100 90 Burst Mode OPERATION PULSE-SKIPPING 60 50 40 60 VOUT2 = 1.8V 20 10 VIN12 = 3.8V VIN12 = 5V 0 0.01 0.1 1 10 IOUT (mA) 100 1000 900 500mA BUCK 800 IOUT3 700 600 500 –50 –25 5mA 0 50 75 25 TEMPERATURE (°C) 100 125 36773 G24 SWITCH IMPEDANCE (Ω) 0.8 VINX = 3.2V 0.7 0.6 500mA NMOS 500mA PMOS 0.5 0.4 800mA PMOS 0.3 0 –50 0.85 0.84 0.84 0.83 0.
LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified Step-Down Switching Regulator 3 Soft-Start and Shutdown OVP Connection Waveform VOUT1 100mV/DIV (AC) 2V VBUS 5V/DIV VOUT3 1V 0V OVGATE 5V/DIV 400mA IL3 200mA 0mA VOUT1 = 1.
LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified OVGATE vs OVSENS LDO Load Step Too Hot BAT Discharge 200 12 OVSENS CONNECTED TO INPUT THROUGH 10 6.2k RESISTOR VNTC < VTOO_HOT 180 VBUS = 0V LDO1 50mV/DIV (AC) 160 140 LDO2 20mV/DIV (AC) 6 4 IOUT1 2 0 IBAT (mA) OVGATE (V) 8 0 2 4 6 INPUT VOLTAGE (V) 8 20 0 CURRENT (mA) BATTERY DISCHARGE CURRENT (mA) 400 125 VBUS = 0V 75 50 60 70 90 100 80 TEMPERATURE (°C) 4.0 VBAT (V) 4.1 4.
LTC3677-3 Pin Functions N-channel MOSFET pass transistor. When the voltage on this pin exceeds a preset level, the OVGATE pin will be pulled to GND to disable the pass transistor and protect downstream circuitry. DVCC (Pin 10): Supply Voltage for I2C Lines. This pin sets the logic reference level of the LTC3677-3. A UVLO circuit on the DVCC pin forces all registers to all 0s whenever DVCC is <1V. Bypass to GND with a 0.1µF capacitor. SDA (Pin 11): I2C Data Input.
LTC3677-3 Pin Functions NTC (Pin 35): The NTC pin connects to a battery’s thermistor to determine if the battery is too hot or too cold to charge. If the battery’s temperature is out of range, charging is paused until it drops back into range. A low drift bias resistor is required from NTCBIAS to NTC and a thermistor is required from NTC to ground. PROG (Pin 36): Charge Current Program and Charge Current Monitor Pin.
LTC3677-3 Block Diagram 8 13 OVSENS OVERVOLTAGE PROTECTON 40 43 34 35 42 OVGATE EXTERNAL POWER DETECT 44 INPUT CURRENT LIMIT CLPROG NTCBIAS BATTERY TEMP MONITOR 15 16 17 10 11 12 21 WALL DETECT NTC CC/CV CHARGER IDEAL DIODE OVERTEMP BATTERY SAFETY DISCHARGER – + + – 15mV IDGATE BAT PROG UVLO ILIM LOGIC EN CHRG 14ms RISING DELAY CHARGE STATUS 14 ACPR VOUT ILIM1 2 41 WALL VBUS ILIM0 1 4 EXTPWR 0.8V 150mA LDO2 – + PUSHBUTTON INPUT ON PBSTAT 0.8V + – DVCC EN 500mA, 2.
LTC3677-3 Operation PowerPath OPERATION Introduction The LTC3677-3 is highly integrated power management IC that includes the following features: – PowerPath controller – Battery charger – Ideal diode – Input overvoltage protection – Pushbutton controller – Three step-down switching regulators – Two low dropout linear regulators Designed specifically for USB applications, the PowerPath controller incorporates a precision input current limit which communicates with the battery charger to ensure that input cu
LTC3677-3 OPERATION support 100% duty cycle operation as well as operating in Burst Mode operation for high efficiency at light load. No external compensation components are required for the switching regulators. The two low dropout regulators can output up to 150mA. All regulators can be programmed for a minimum output voltage of 0.8V and can be used to power a microcontroller core, microcontroller I/O, memory or other logic circuitry.
LTC3677-3 OPERATION Ideal Diode from BAT to VOUT The LTC3677-3 has an internal ideal diode as well as a controller for an optional external ideal diode. Both the internal and the external ideal diodes respond quickly whenever VOUT drops below BAT. If the load increases beyond the input current limit, additional current will be pulled from the battery via the ideal diodes.
LTC3677-3 OPERATION VBUS Undervoltage Lockout (UVLO) and Undervoltage Current Limit (UVCL) An internal undervoltage lockout circuit monitors VBUS and keeps the input current limit circuitry off until VBUS rises above the rising UVLO threshold (3.8V) and at least 50mV above VOUT . Hysteresis on the UVLO turns off the input current limit if VBUS drops below 3.7V or 50mV below VOUT . When this happens, system power at VOUT will be drawn from the battery via the ideal diode.
LTC3677-3 OPERATION In either the constant-current or constant-voltage charging modes, the PROG pin voltage will be proportional to the actual charge current delivered to the battery.
LTC3677-3 OPERATION pause charging when the resistance of the NTC thermistor drops to 0.54 times the value of R25 or approximately 54k (for a Vishay curve 1 thermistor, this corresponds to approximately 40°C). If the battery charger is in constantvoltage (float) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. As the temperature drops, the resistance of the NTC thermistor rises.
LTC3677-3 OPERATION or by adding a second adjustment resistor to the circuit. If only the bias resistor is adjusted, then either the upper or the lower threshold can be modified but not both. The other trip point will be determined by the characteristics of the thermistor.
LTC3677-3 OPERATION are linked. Therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the IC. Consider an example where a 60°C hot trip point is desired. From the Vishay curve 1 R-T characteristics, rHOT is 0.2488 at 60°C. Using the above equation, RNOM should be set to 46.4k. With this value of RNOM, the cold trip point is about 16°C. Notice that the span is now 44°C rather than the previous 40°C.
LTC3677-3 OPERATION Dual Input Overvoltage Protection Reverse Input Voltage Protection It is possible to protect both VBUS and WALL from overvoltage damage with several additional components, as shown in Figure 5. Schottky diodes D1 and D2 pass the larger of V1 and V2 to R1 and OVSENS. If either V1 or V2 exceeds 6V plus VF(SCHOTTKY), OVGATE will be pulled to GND and both the WALL and USB inputs will be protected. Each input is protected up to the drain-source breakdown, BVDSS, of MN1 and MN2.
LTC3677-3 OPERATION The power good status bits of LDO1 and LDO2 are available in I2C through the read-back registers PGLDO[1] and PGLDO[2] for LDO1 and LDO2 respectively. The power good comparators for both LDOs are sampled when the I2C port receives the correct I2C read address. Figure 7 shows the LDO application circuit.
LTC3677-3 OPERATION Typical values for R1 are in the range of 40k to 1M. The capacitor CFB cancels the pole created by feedback resistors and the input capacitance of the FB pin and also helps to improve transient response for output voltages much greater than 0.8V. A variety of capacitor sizes can be used for CFB but a value of 10pF is recommended for most applications. Experimentation with capacitor sizes between 2pF and 22pF may yield improved transient response.
LTC3677-3 OPERATION Dropout Operation Slew Rate Control It is possible for a step-down switching regulator’s input voltage to approach its programmed output voltage (e.g., a battery voltage of 3.4V with a programmed output voltage of 3.3V). When this happens, the P-Channel MOSFET switch duty cycle increases until it is turned on continuously at 100%.
LTC3677-3 OPERATION Low Supply Operation An undervoltage lockout circuit on VOUT (VOUT UVLO) shuts down the step-down switching regulators when VOUT drops below about 2.7V. It is recommended that the stepdown switching regulator input supplies (VIN12, VIN3) be connected to the power path output (VOUT) directly. This UVLO prevents the step-down switching regulators from operating at low supply voltages where loss of regulation or other undesirable operation may occur.
LTC3677-3 OPERATION choice of which style inductor to use often depends more on the price versus size, performance, and any radiated EMI requirements than on what the step-down switching regulators requires to operate. The inductor value also has an effect on Burst Mode operation. Lower inductor values will cause Burst Mode switching frequency to increase. Table 3 shows several inductors that work well with the step-down switching regulators.
LTC3677-3 OPERATION ADDRESS DATA BYTE A WR A7 0 0 0 1 0 0 1 0 SDA 0 0 0 1 0 0 1 0 ACK SCL 1 2 3 4 5 6 7 8 9 A6 A5 A4 A3 DATA BYTE B A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 START STOP ACK 1 2 3 4 5 6 7 8 9 ACK 1 2 3 4 5 6 7 8 9 SDA tSU, DAT tLOW tSU, STA tHD, DAT tBUF tSU, STO tHD, STA SCL tHIGH tHD, STA START CONDITION tr tSP tf REPEATED START CONDITION STOP CONDITION START CONDITION 36773 F11 Figure 11.
LTC3677-3 OPERATION I2C Bus Write Operation The master initiates communication with the LTC3677-3 with a START condition and the LTC3677-3’s write address. If the address matches that of the LTC3677-3, the LTC3677-3 returns an acknowledge. The master should then deliver the sub-address. Again the LTC3677-3 acknowledges and the cycle is repeated for the data byte. The data byte is transferred to an internal holding latch upon the return of its acknowledge by the LTC3677-3.
LTC3677-3 OPERATION tions indicates that the condition is true. For example, 1 read back from bit A3 indicate that LDO1 is enabled and regulating correctly. A status read from the LTC3677-3 captures the status information when the LTC3677-3 acknowledge its read address. Table 6.
LTC3677-3 OPERATION Pushbutton Interface Operation PBSTAT Operation State Diagram/Operation PBSTAT goes LOW 50ms after the initial pushbutton application (ON LOW) and will stay low for 50ms minimum. PBSTAT will go HIGH coincident with ON going HIGH unless ON goes HIGH before the 50ms minimum LOW time. Figure 13 shows the LTC3677-3 pushbutton state diagram.
LTC3677-3 OPERATION Power-Up via Pushbutton Timing Power-Up via PWR_ON Timing The timing diagram, Figure 13, shows the LTC3677-3 powering up through application of the external pushbutton. For this example the pushbutton circuitry starts in the POFF state with VOUT not in UVLO and Buck1, Buck2 and LDO2 disabled. Pushbutton application (ON LOW) for 50ms transitions the pushbutton circuitry into the PUP state which sequences up LDO2, Buck1 and Buck2 in that order.
LTC3677-3 OPERATION Power Down via Pushbutton Timing VOUT UVLO Power-Down Timing The timing diagram, Figure 15, shows the LTC3677-3 powering down by μC/μP control. For this example the pushbutton circuitry starts in the PON state with VOUT not in UVLO and Buck1, Buck2 and LDO2 enabled. In this case the pushbutton is applied (ON LOW) for at least 50ms, which generates a low impedance on the PBSTAT output. After receiving the PBSTAT the μC/μP will drive the PWR_ON input LOW.
LTC3677-3 OPERATION Hard Reset Timing Power-Up Sequencing Hard reset provides a way to reset the μC/μP in case of a software lockup. To initiate a hard reset, the pushbutton is pressed (ON LOW) and held for greater than 14 seconds. Once the hard reset time is exceeded the PGOOD input will go LOW for 1.8ms which resets the μC/μP. Operation of the enabled supplies is not effected by the hard reset event.
LTC3677-3 OPERATION Layout and Thermal Considerations Printed Circuit Board Power Dissipation In order to be able to deliver maximum charge current under all conditions, it is critical that the exposed ground pad on the backside of the LTC3677-3 package be soldered to a ground plane on the board. Correctly soldered to 2500mm2 ground plane on a double-sided 1oz copper board the LTC3677-3 has a thermal resistance (θJA) of approximately 45°C/W.
LTC3677-3 OPERATION Consider the previous example with an ambient temperature of 55°C. The charge current will be reduced to approximately: 110°C – 55°C – 0.3W 45°C/W IBAT = 5V – 3.3V IBAT = 1.22 – 0.3W = 542mA 1.7 V Printed Circuit Board Layout When laying out the printed circuit board, the following list should be followed to ensure proper operation of the LTC3677-3: 1. The exposed pad of the package (Pin 45) should connect directly to a large ground plane to minimize thermal and electrical impedance.
LTC3677-3 Typical Application 5V WALL ADAPTER 4 13 8 40 USB WALL ACPR OVGATE OVSENSE 2.1k 43 PROG CLPROG 10 DVCC 11 SDA 12 SCL 499k µC/µP VIN12 LTC3677-3 36 DVCC SDA SCL 499k EXTPWR PBSTAT PWR_ON 30 VINLDO2 27 VINLDO1 39 VOUT VBUS 10µF 2k Si2333DS 41 VIN3 10µF 2.2µF 32 6 2.
LTC3677-3 Package Description UFF Package Variation: UFFMA UFFMA Package 44-Lead Plastic QFN (4mm × 7mm) 44-Lead Plastic QFN (4mm s 7mm) (Reference LTC DWG # 05-08-1762 Rev Ø) (Reference LTC DWG # 05-08-1762 Rev Ø) 1.48 ±0.05 0.70 ±0.05 4.50 ±0.05 3.10 ±0.05 2.40 REF 1.70 ±0.05 2.56 ±0.05 2.02 ±0.05 2.76 ±0.05 2.64 ±0.05 0.98 ±0.05 PACKAGE OUTLINE 0.20 ±0.05 5.60 REF 6.10 ±0.05 7.50 ±0.05 0.40 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p0.10 0.75 p0.
LTC3677-3 Typical application Si2333DS 5V WALL ADAPTER Si2306BDS D3 5.6V 4 R1 500k 13 6.2k 8 OPTIONAL OVERVOLTAGE/ REVERSE VOLTAGE PROTECTION 40 10µF 2k 36 2.1k 43 10 11 12 DVCC SDA SCL 499k 499k EXTPWR PBSTAT PWR_ON VINLDO1 OVSENSE VOUT USB µC/µP WALL ACPR OVGATE Si2333DS 41 39 10µF 2.2µF 32 VBUS VIN12 2.
