Datasheet

LTC3676/LTC3676-1
26
3636fa
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OPERATION
I
2
C Slave Address
The LTC3676 responds to factory programmed read and
write addresses. The least significant bit of the address byte
is 0 when writing data and 1 when reading data. Table 19
shows read and write addresses for the LTC3676 options.
Table 19. LTC3676 and LTC3676-1 I
2
C Read and Write
Addresses
LT C PART NUMBER R/W ADDRESS
LTC3676 W 0111 1000, 0x78
LTC3676 R 0111 1001, 0x79
LTC3676-1 W 0111 1010, 0x7A
LTC3676-1 R 0111 1011, 0x7B
I
2
C Write Operation
The LTC3676 has twenty-two command registers for
control input. They are accessed by the I
2
C port via a
sub-addressed writing system.
A single write cycle of the LTC3676 consists of exactly
three bytes except when a clear interrupt or hard reset
command is written. The first byte is always the LTC3676
write address. The second byte represents the LTC3676
sub-address. The sub-address is a pointer which directs
the subsequent data byte within the LTC3676. The third
byte consists of the data to be written to the location
pointed to by the sub-address.
As shown in Figure 15, the LTC3676 supports multiple
sub-addressed write operations. Data pairs sent following
the chip write address are interpreted as sub-address and
data. Any number of sub-address and data pairs may be
sent. The data in the command registers is not acted on
by the LTC3676 until a STOP signal is issued.
The LTC3676 will keep interim writes to the registers
when
a
repeat START condition occurs. A repeat start may be
used to set up other devices on the I
2
C bus prior to send-
ing a STOP condition. The LTC3676 will act on the data
written
prior to the repeat start when a STOP condition
is detected.
I
2
C Read Operation
Figure 16 shows the LTC3676 command register read
sequence. The bus master reads a byte of data from a
LTC3676 command or status register by first writing the
LTC3676 write address followed by the sub-address to
be read from. The LTC3676 acknowledges each of the
two bytes. Next, the bus master initiates a new START
condition and sends the LTC3676 read address. Follow
-
ing the
acknowledge of the read address by the LTC3676,
the
LTC3676 pushes data onto the I
2
C bus for the 8 clock
cycles. The bus master then acknowledges the data on
its ninth clock.
The last read sub-address that is written to the LTC3676
is stored. This allows repeated polling of a command or
status register without the need to re-write its sub-address.
Additionally, the last register written may be immedi
-
ately read by issuing a START condition followed by read
address and clocking out the data.
Figure 14. LTC3676 I
2
C Serial Port Timing
t
SU, DAT
t
HD, STA
t
HD, DAT
SDA
SCL
t
SU, STA
t
HD, STA
t
SU, STO
3676 F14
t
BUF
t
LOW
t
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
t
SP