Datasheet

LTC3676/LTC3676-1
20
3636fa
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OPERATION
keeping the processor from driving PWR_ON, then the
LTC3676 will pull WAKE low, shut off all regulators, and
enter the STANDBY state. The STANDBY state is also a
low power, 12µA (typical) state.
Table 9. Register, Enable, WAKE Control During Operating
Mode State Control
STATE REGISTERS ENABLES WAKE
POR/HRST DEFAULT R/W Inhibited LOW
5 SEC PWR_ON TIMER R/W Allowed HIGH
ON R/W Allowed HIGH
1 SEC OFF TIMER HRST Set to POR
Defaults
Sequence Down LOW
1 SEC OFF TIMER
STANDBY
I
2
C Enable
and SW
Mode Bits
Cleared
Sequence Down LOW
STANDBY R/W Inhibited LOW
Power Down Using Pushbutton
When in the ON state, the system controller is responsible
for deciding what action to take when a pushbutton event
occurs. By monitoring the IRQ status pin and IRQSTAT[0]
status register bit, the controller can detect a pushbutton
request. If a power-down into standby state is desired
then the controller should drive PWR_ON low and set
command register bit CNTRL[7] low.
Button Status Indication
When a pushbutton pulls ON low for 50ms in the ON state,
IRQ is pulled low and the PB status bit in the IRQSTAT[0]
status register is set. IRQ and the IRQSTAT status bit are
active while ON is low or for a minimum of 50ms.
Power Up and Down with PWR_ON
The PWR_ON pin is an alternative way to power up the
LTC3676 instead of using the ON pin. When PWR_ON is
driven high or
command register
CNTRL[7] is set high,
WAKE is pulled HIGH and the LTC3676 passes through
the 5 second PWR_ON timer to the ON state. Figure 9
shows PWR_ON and WAKE timing. WAKE stays high for
a minimum of 5 seconds.
Figure 8. Power-Down Using Pushbutton
50ms
IRQSTAT[0]
WAKE
<10 SEC
ON (PB)
IRQ
PWR_ON
(PIN OR I
2
C)
3676 F08
µC/µP CONTROL
3ms
Figure 7. Power Up Using Pushbutton
400ms
ON (PB)
WAKE
PWR_ON
(PIN OR I
2
C)
<5 SEC
3676 F07
µC/µP CONTROL
Figure 9. Power Up and Down with PWR_ON
PWR_ON
(PIN OR I
2
C)
WAKE
3676 F09
µC/µP CONTROL
5 SEC
3ms
3ms
POWER ON SEQUENCING
Enable Pin Operation
The LTC3676 enable pins facilitate pin-strapping output
rails to enable pins to up-sequence the LTC3676 regulators
in any order. Figure 10 shows an example of pin-strapped
sequence connections. The enable pins normally have a
0.8V (typical) input voltage threshold.
If any enable is driven high, the remaining enable input
thresholds switches to an accurate 400mV threshold. To
ensure separation of the sequenced rails, there is a built-
in 450µs delay from the enable pin threshold crossing to
the internal enable of the regulator. Figure 11 shows the
start-up timing of the example shown in Figure 10.