Datasheet

LTC3676/LTC3676-1
19
3676fa
For more information www.linear.com/LTC3676
OPERATION
Table 8. Buck1, Buck2, Buck3, and Buck4 Slewing DAC Control
Command Registers
COMMAND
REGISTER[BIT] VALUE SETTING
DVB1A[4:0] bbbbb Buck1 Reference DAC Input A
DVB1A[5] 0*
1
Select DVB1A[4:0]
Select DVB1B[4:0]
DVB1B[4:0]
bbbbb Buck1 Reference DAC Input B
DVB1B[5] 0*
1
Pull PGOOD Low Slewing Buck1
Do Not Pull PGOOD Slewing Buck1
DVB2A[4:0]
bbbbb Buck2 Reference DAC Input A
DVB2A[5] 0*
1
Select DVB2A[4:0]
Select DVB2B[4:0]
DVB2B[4:0]
bbbbb Buck2 Reference DAC Input B
DVB2B[5] 0*
1
Pull PGOOD Low Slewing Buck2
Do Not Pull PGOOD Slewing Buck2
DVB3A[4:0]
bbbbb Buck3 Reference DAC Input A
DVB3A[5] 0*
1
Select DVB3A[4:0]
Select DVB3B[4:0]
DVB3B[4:0]
bbbbb Buck3 Reference DAC Input B
DVB3B[5] 0*
1
Pull PGOOD Low Slewing Buck3
Do Not Pull PGOOD Slewing Buck3
DVB4A[4:0]
bbbbb Buck4 Reference DAC Input A
DVB4A[5] 0*
1
Select DVB4A[4:0]
Select DVB4B[4:0]
DVB4B[4:0]
bbbbb Buck4 Reference DAC Input B
DVB4B[5] 0*
1
Pull PGOOD Low Slewing Buck4
Do Not Pull PGOOD Slewing Buck4
*denotes default power-on value.
PUSHBUTTON OPERATION
Operating Mode State Diagram
Figure 6 shows the state diagram of the LTC3676 enable
and sequence controller. First application of power to
V
IN
pin brings the controller to the power-on reset/hard
reset (POR/HRST) state. In this state the I
2
C command
registers have been set to their default values, only LDO1
is operating, and the device is waiting for pushbutton or
PWR_ON inputs. Regulator enable pins and command
register enable bits are ignored in POR/HRST state. In the
POR/HRST state V
IN
draws typically 12µA.
Power Up Using Pushbutton
When the ON pin is held low for 400ms the WAKE pin is
pulled high, enable pins are recognized, and the five second
PWR_ON timer is started. If in the ON state and PWR_ON
is low or a fault is detected, then WAKE is brought low and
after a 1 second power-down time, the STANDBY state
is entered. In STANDBY, the enable bits in the command
registers are cleared and enable pins are ignored. Table9
shows the control of command registers, enables, and
WAKE at each state.
The 5 second power-on state is intended for the system to
detect that power rails are correct and either drive PWR_ON
pin high or set command register bit CNTRL[7] high to
keep the rails active. If there were a
system level problem
Figure 6. LTC3676 Operating Mode State Diagram
ENABLE
ALLOWED AND
WAKE HIGH
ENABLE
INHIBITED AND
WAKE LOW
POR/HRST
V
IN
HIGH
ON 400ms
OR PWR_ON
ON 10 SEC
OR I
2
C HRST
ON 400ms
OR PWR_ON
PWR_ON
OR FAULT
ON 10 SEC
OR I
2
C HRST
ON 10 SEC
OR I
2
C HRST
1 SEC OFF
TIMER
HRST
3676 F06
1 SEC OFF
TIMER
STANDBY
5 SEC
PWR_ON
TIMER
ON
STANDBY