Datasheet

LTC3676/LTC3676-1
10
3636fa
For more information www.linear.com/LTC3676
PIN FUNCTIONS
FB_L2 (Pin 1): Feedback Input for LDO2. Set full-scale
output voltage using a resistor divider connected from
LDO2 to this pin to ground.
V
IN_L2
(Pin 2): Power Input for LDO2. This pin should be
bypassed to ground with aF or greater ceramic capacitor.
Voltage on V
IN_L2
should not exceed voltage on V
IN
pin.
LDO2 (Pin 3): Output Voltage of LDO2. Nominal output
voltage is set with a resistor feedback divider that servos
to a fixed 725mV reference. This pin must be bypassed to
ground with a 1µF or greater ceramic capacitor.
LDO3 (Pin 4): Output Voltage of LDO3. Nominal output
voltage is a fixed 1.8V. This pin must be bypassed to
ground with a 1µF or greater ceramic capacitor.
V
IN_L3
(Pin 5): Power Input for LDO3. This pin should be
bypassed to ground with aF or greater ceramic capacitor.
Voltage on V
IN_L3
should not exceed voltage on V
IN
pin.
LDO4 (Pin 6): Output Voltage of LDO4. Nominal output
voltage is set with a resistor feedback divider that servos
to a fixed 725mV reference. This pin must be bypassed to
ground with a 1µF or greater ceramic capacitor.
V
IN_L4
(Pin 7): Power Input for LDO4. This pin should be
bypassed to ground with aF or greater ceramic capacitor.
Voltage on V
IN_L4
should not exceed voltage on V
IN
pin.
FB_L4 (Pin 8): Feedback Input for LTC3676 LDO4. Set
full-scale output voltage using a resistor divider connected
from LDO4 to this pin to ground.
VDDQIN (Pin 8): V
DD
Sense Input for LTC3676-1. Tie DDR
memory V
DD
supply to this pin.
EN_L4 (Pin 9): Enable LDO4 Input for LTC3676. Active
high enables LDO4. A weak pull-down pulls EN_L4 low
when left floating.
VTTR (Pin 9): DDR V
REF
Output Pin for LTC3676-1. Buff-
ered reference
equal to one-half VDDQIN voltage on Pin 8.
EN_L3 (Pin 10): Enable LDO3 Input. Active high enables
LDO3. A weak pull-down pulls EN_L3 low when left floating.
SW4 (Pin 11): Switch Pin for Step-Down Switching Regula
-
tor 4. Connect one
side of step-down switching regulator
4 inductor to this pin.
DV
DD
(Pin 12): Supply Voltage for I
2
C Serial Port. This
pin sets the logic reference level of SCL and SDA I
2
C pins.
DV
DD
resets I
2
C registers to power-on state when driven
to <1V. SCL and SDA logic levels are scaled to DV
DD
. Con-
nect a
0.1µF decoupling capacitor from this pin to ground.
SDA (Pin 13): Data Pin for the I
2
C Serial Port. The I
2
C
logic levels are scaled with respect to DV
DD
.
SCL (Pin 14): Clock Pin for the I
2
C Serial Port. The I
2
C
logic levels are scaled with respect to DV
DD
.
PV
IN4
(Pin 15): Power Input for Step-Down Switching
Regulator 4. Tie this pin to V
IN
supply. This pin should
be bypassed to ground with a 10μF or greater ceramic
capacitor.
PV
IN3
(Pin 16): Power Input for Step-Down Switching
Regulator 3. Tie this pin to the V
IN
supply. This pin should
be bypassed to ground with a 10μF or greater ceramic
capacitor.
EN_B4 (Pin 17): Enable Step-Down Switching Regulator4 .
Active high input enables step-down switching regulator4 .
A weak pull-down pulls EN_B4 low when left floating.
EN_B3 (Pin 18): Enable Step-Down Switching Regulator3 .
Active high input enables step-down switching regulator3 .
A weak pull-down pulls EN_B3 low when left floating.
VSTB (Pin 19): Voltage Standby. When VSTB is low,
the DAC registers are selected by
command register
bit
DVBxA[5]. When VSTB is high, the DAC registers are
forced to DVBxB registers. Tie VSTB to ground if unused.
SW3 (Pin 20): Switch Pin for Step-Down Switching
Regulator 3. Connect one side of step-down switching
regulator3 inductor to this pin.
PWR_ON (Pin 21): External Power On. Handshaking pin
to acknowledge successful power-on sequence. PWR_ON
must be driven high within five seconds of WAKE going
high to keep power on. PWR_ON can be used to activate
the WAKE output by driving high. Drive low to shut down
WAKE.
FB_B3 (Pin 22): Feedback Input for Step-Down Switching
Regulator 3. Set full-scale output voltage using resistor
divider connected from the output of step-down switching
regulator 3 to this pin to ground.