Datasheet

LTC3675/LTC3675-1
31
36751fc
For more information www.linear.com/LTC3675
applicaTions inForMaTion
Status Byte Read Back
When either the RSTB or IRQB pin is pulled low, it indicates
to the user that a fault condition has occurred. To find out
the exact nature of the fault, the user can read the status reg-
isters. There are two status registers. One register provides
real time fault condition reporting while a second register
latches data when an interrupt has occurred. Figure 4
shows the operation of the real time and latched status
registers. The contents of the latched status register are
cleared when a CLRINT signal is issued. A PGOOD bit is
a ‘0’ if that regulator’s output voltage is more than 8%
below its programmed value.
The sub-address for the real time status register is 0Ch
and its format is as follows:
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Unused Unused PGOOD6 PGOOD5 PGOOD4 PGOOD3 PGOOD2 PGOOD1
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
UV OT PGOOD6 PGOOD5 PGOOD4 PGOOD3 PGOOD2 PGOOD1
The sub-address for the latched status register is 0Dh and
its format is as follows:
A write operation cannot be performed to either of the
status registers.
PCB Considerations
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3675/LTC3675-1:
1. The exposed pad of the package (pin 45) should connect
directly to a large ground plane to minimize thermal and
electrical impedance.
2. All the input supply pins must be tied together and each
supply pin should have a decoupling capacitor.
3. The switching regulator input supply pins and their re-
spective decoupling capacitors should be kept as short
as possible. The GND side of these capacitors should