Datasheet

LTC3675/LTC3675-1
21
36751fc
For more information www.linear.com/LTC3675
operaTion
POWER-UP AND POWER-DOWN VIA ENABLE PIN OR I
2
C
With the LTC3675/LTC3675-1 in its off state, a regulator
can be enabled either via its enable pin or I
2
C. In Figure 2c,
buck regulator 1 is enabled via its enable pin at time t
1
.
The WAKE pin goes HIGH for 5 seconds and at t
2
is pulled
LOW. The buck regulator stays enabled until time t
3
when
a hard reset command is issued via I
2
C. The buck regula-
tor powers down and stays off for 1 second. At time t
4
,
the LTC3675/LTC3675-1 exit from the power down state.
Since the buck regulator 1 is still enabled via its enable
pin, it powers back up. WAKE also gets pulled HIGH for
5 seconds. The RSTB pin gets pulled HIGH 200ms after
the buck regulator 1 is in its PGOOD state.
LED CURRENT PROGRAMMING
The LED current is primarily controlled through the LED
DAC register at I
2
C sub-address 8. This register controls
an 8 bit current DAC. A 20k resistor placed between the
LED_FS pin and ground provides a current reference for
the DAC which results in 98µA of programmed LED current
per LSB. For example,
programming a LED DAC
register
code of 64h will result in a LED current of 9.8mA and a
full-scale setting of FFh will result in a LED current of 25mA.
The 2xFS bit which is bit 3 of the LED configuration register
at sub-address 7 effectively doubles the programmed LED
current. With a 20k resistor from LED_FS to ground each
LSB will be 196µA. Programming a LED DAC register
code of 64h will result in a LED current of 19.6mA and
a full-scale setting of FFh will result in an LED current of
50mA. The 2xFS mode is only intended for use when the
output voltage is below 20V.
I
2
C INTERFACE
The LTC3675/LTC3675-1 may communicate with a bus
master using the standard I
2
C 2-wire interface. The timing
diagram (Figure 3) shows the relationship of the signals
on the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines. The LTC3675/LTC3675-1 are
both a slave receiver and slave transmitter. The I
2
C control
signals, SDA and SCL are scaled internally to the DV
CC
supply. DV
CC
should be connected to the same power
supply as the bus pull-up resistors.
The I
2
C port has an undervoltage lockout on the DV
CC
pin.
When DV
CC
is below 1V, the I
2
C serial port is cleared and
the LTC3675/LTC3675-1 registers are set to their default
configurations.
I
2
C Bus Speed
The I
2
C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I
2
C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
Figure 3. I
2
C Bus Operation
t
SU, DAT
t
HD, STA
t
HD, DAT
SDA
SCL
t
SU, STA
t
HD, STA
t
SU, STO
36751 F03
t
BUF
t
LOW
t
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
t
SP
ACK ACK
1 2 3
ADDRESS WR
4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
0 0 0 1 0 0 1 0
0 0 0 1 0 0 1 0
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
ACK
STOPSTART
SDA
SCL
DATA BYTE A DATA BYTE B