Datasheet

LTC3646/LTC3646-1
18
36461fa
For more information www.linear.com/LTC3646
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 +…)
where L1, L2, etc. are the individual loss terms as a per
-
centage of input power.
Although all dissipative elements in the circuit produce
losses, three main sources account for the majority of the
losses in the LTC3646: 1) I
2
R loss, 2) switching losses
and quiescent current loss, 3) transition losses and other
system losses.
1. I
2
R loss is calculated from the DC resistance of the
internal switches, R
SW
, and external inductor, R
L
. In
continuous mode, the average output current will flow
through inductor L but is chopped between the internal
top and bottom power MOSFETs. Thus, the series resis
-
tance looking
into the SW pin is a function of both the
top and bottom MOSFET’s R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) +(R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the curves in the Typical Performance
Characteristics section. Thus to obtain I
2
R loss:
I
2
R Loss = I
OUT
2
• (R
SW
+ R
L
)
2. The internal LDO supplies the power to the INTV
CC
rail.
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is a cur-
rent out of INTV
CC
that is typically much larger than
the DC control bias current. In continuous mode,
I
GATECHG
= f
O
(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate
charges of the internal top and bottom power MOSFETs
and f
O
is the switching frequency. For estimation
purposes, (Q
T
+ Q
B
) on the LTC3646 is approximately
5nC. To calculate the total power loss from the LDO
load, simply add the gate charge current and quiescent
current and multiply by V
IN
:
P
LDO
= (I
GATECHG
+ I
Q
) • SVIN
As will be discussed below, in certain cases the overall
efficiency can be
improved by supplying the gate and
quiescent current through the EXT
V
CC
pin.
3. Other hidden losses such as transition loss, copper trace
resistances, and internal load currents can account for
additional efficiency degradations in the overall power
system. Transition loss arises from the brief amount of
time the top power MOSFET spends in the saturated
region during switch node transitions. Other losses,
including diode conduction losses during dead time
and inductor core losses, generally account for less
than 2% total additional loss.
Transition loss can become significant at high V
IN
or high
switching frequencies. Transition loss for the LTC3646 can
be approximated by the following formula:
Loss (Watts) = I
OUT
• V
IN
2
• f
O
• 10
–10
applicaTions inForMaTion