Datasheet

LTC3634
23
3634fb
For more information www.linear.com/LTC3634
C
OUT
should be closely connected to both PGND and
the (–) plate of C
IN
.
3. The resistive divider, (e.g. R1 and R2 in Figure 1) must
be connected between the (+) plate of C
OUT
and a
ground line terminated near SGND. The feedback signal
V
FB
should be routed away from noisy components
and traces, such as the SW line, and its trace length
should be minimized. In addition, the R
T
resistor and
loop compensation components should be terminated
to SGND.
4. Keep sensitive components away from the SW pin.
The R
T
resistor, the compensation components, the
feedback resistors, and the INTV
CC
bypass capacitor
should all be routed away from the SW trace and the
inductor L.
5. A ground plane is preferred, but if not available, the
signal and power grounds should be segregated with
both connecting to a common, low noise reference point.
The connection to the PGND pin should be made with
a minimal resistance trace from the reference point.
6. Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside of the package (PGND). Refer to Figures 10
and 11 for board layout examples.
Design Example
As a design example, consider using the LTC3634 (as shown
in Figure 1) to power DDR2 SDRAM with the following
specifications: V
IN(MAX)
= 13.2V, I
OUT(MAX)
= ±2A, f = 1MHz,
V
DROOP(VDDQ)
< 60mV, V
DROOP(VTT
) < 30mV. The following
discussion will use equations from the previous sections.
First, the correct R
T
resistor value for 1MHz switching
frequency must be chosen. Based on previous discus-
sions, R
T
is calculated to be
R
T
=
3.2E
11
f






= 320kΩ
The closest standard value is 324k.
Next, select values for R1 and R2 to set channel 1 (V
DDQ
)
to be 1.8V for DDR2 SDRAM. Choosing R1 to be 12.1k,
R2 is calculated to be:
R2=12.1k •
1.8V
0.6V
−1






= 24.2k
The closest standard value is 24.3k. Tying VDDQIN to
V
OUT1
sets V
OUT2
to be half of V
OUT1
.
Next, we can pick inductor values for both the V
DDQ
and
V
TT
outputs. Choosing inductor current ripple to be 1A
at maximum V
IN
:
L1=
1.8V
1MHz •1A






1−
1.8V
13.2V






=1.55µH
L2 =
0.9V
1MHz •1A






1−
0.9V
13.2V






= 0.838µH
Standard values of 1.5μH and 0.82µH should be used.
Ceramic caps will be used for C
OUT
and will be selected
based on the charge storage requirement. Assuming a
worst case 4A load step (–2A to 2A):
C
OUT1
≈
3• 4A
1MHz •60mV
= 200µF
C
OUT2
≈
3• 4A
1MHz •30mV
= 400µF
Lastly, we will choose compensation components. Choos-
ing the crossover frequency f
C
= 50kHz:
R
COMP1
=
2π •50kHz •200µF
1mΩ
−1
•7Ω
−1






1.8V
0.6V






= 27kΩ
R
COMP2
=
2π •50kHz • 400µF
1mΩ
−1
•7Ω
−1






0.9V
0.9V






=18kΩ
Choosing the zero frequency to be 10kHz yields C
COMP1
=
589pF and C
COMP2
= 884pF. The closest standard values
for the compensation components are 26.7k, 18k, 560pF
and 910pF, respectively.
The final circuit is shown in Figure 9.
applicaTions inForMaTion