Datasheet

LTC3634
12
3634fb
For more information www.linear.com/LTC3634
applicaTions inForMaTion
A general LTC3634 application circuit is shown in Figure 1.
External component selection is largely driven by the load
requirement and switching frequency.
Component selec-
tion typically begins with selecting the feedback resistors
to set the desired output voltage. Next the inductor L and
resistor R
T
are selected. Once the inductor is chosen, the
input capacitor (C
IN
) and the output capacitor (C
OUT
) can
be selected. Finally, the loop compensation components
may be selected to stabilize the step-down regulator. The
remaining optional external components can then be se
-
lected for functions such as loop compensation, TRACKSS,
V
IN
, UVLO, and PGOOD.
Programming Switching Frequency
Selection of the switching frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but generally requires
larger inductance and capacitance values to maintain low
output ripple voltage. Connecting a resistor from the RT
pin to SGND programs the switching frequency (f) between
500kHz and 4MHz according to the following formula:
R
RT
=
3.2E
11
f
where R
RT
is in Ω and f is in Hz.
RUN1
RUN2
RT
INTV
CC
PHMODE
MODE/SYNC
ITH1
ITH2
LTC3634
3634 F01
L1
R2
R1
0.1µF
C3
0.01µF
0.1µF
PGNDSGND
BOOST1
SW1
V
ON1
VDDQIN
V
FB1
BOOST2
SW2
V
FB2
V
ON2
VTTR
V
IN1
V
IN
3.6V TO 15V
V
IN2
L2
R
COMP2
R
RT
C
OUT1
V
DDQ
C
OUT2
V
TT
C5
(OPT)
C
COMP2
R
COMP1
C
COMP1
C2
2.2µF
C1
C4
(OPT)
V
REF
Figure 1. Typical Application Circuit for DDR Memory Supply
pulses to be drawn from the input capacitor and supply
at the same time. When running the LTC3634 channels
out-of-phase, the large current pulses are interleaved,
effectively reducing the amount of time the pulses overlap.
Thus, the total RMS input current is decreased, which both
relaxes the capacitance requirements for the V
IN
bypass
capacitors and reduces the voltage noise on the supply line.
One potential disadvantage to this configuration occurs
when one channel is operating at 50% duty cycle. In this
situation, SW node transitions can potentially couple from
one channel to the other, resulting in frequency jitter on
one or both channels. This effect can be mitigated with a
well designed board layout. Alternatively, tying PHMODE
low changes the phase difference to be 90°, which may
prevent SW1 and SW2 from transitioning at the same
point in time.
operaTion