Datasheet

LTC3630
20
3630fc
Pin Clearance/Creepage Considerations
The LTC3630 is available in two packages (MSE16 and
DHC) both with identical functionality. However, the 0.2mm
(minimum space) between pins and paddle on the DHC-
package may not provide sufficient PC board trace clearance
between high and low voltage pins in some higher voltage
applications. In applications where clearance is required,
APPLICATIONS INFORMATION
V
FB
I
SET
SW
L1
33µH
V
IN
RUN
FBO
C
OUT
100µF
×2
C
IN
4.7µF
C
ISET
100pF
R
ISET
220k
C
IN
: TDK C5750X7R2A-475M (2220)
C
OUT
: 2 × AVX 1812D107MAT
L1: SUMIDA CDRH105RNP-330N
V
OUT
5V
500mA
V
IN
5V TO 65V
3630 F13
SS
V
PRG1
V
PRG2
GND
LTC3630
Figure 13. 5V to 65V Input to 5V Output,
High Efficiency, 500mA Regulator
V
FB
I
SET
SW
L1
V
IN
RUN
R3
R1
R2
C
IN
C
OUT
V
OUT
V
IN
R4
R
ISET
C
ISET
C
SS
3630 F12
FBO
SS
V
PRG2
V
PRG1
LTC3630
VIAS TO GROUND PLANE
OUTLINE OF LOCAL GROUND PLANE
V
OUT
V
IN
GND
GND
L1
C
OUT
C
IN
Figure 12. Example PCB Layout
the MSE16 package should be used. The MSE16 package
has removed pins between all the adjacent high voltage
and low voltage pins, providing 0.657mm clearance which
will be sufficient for most applications. For more informa-
tion, refer to the printed circuit board design standards
described in IPC-2221 (www.ipc.org).