Datasheet

LTC3630
17
3630fc
APPLICATIONS INFORMATION
Higher Current Applications
For applications that require more than 500mA, the
LTC3630 provides a feedback comparator output pin
(FBO) for driving additional LTC3630s. When the FBO pin
of a “master” LTC3630 is connected to the V
FB
pin of one
or more “slave” LTC3630s, the master controls the burst
cycle of the slaves.
Figure 10 shows an example of a 5V, 1A regulator using
two LTC3630s. The master is configured for a 5V fixed
output with external soft-start and the V
IN
UVLO level is
set by the RUN pin. Since the slaves are directly controlled
by the master, the SS pin of the slave should have minimal
capacitance and the RUN pin of the slave should be floating.
Furthermore, slaves should be configured for a 1.8V fixed
output (V
PRG1
= V
PRG2
= SS) to set the V
FB
pin threshold at
1.8V. The inductors L1 and L2 do not necessarily have to
be the same, but should both meet the criteria described
above in the Inductor Selection section.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V
IN
operating current and I
2
R losses. The V
IN
operating current dominates the efficiency loss at very
low load currents whereas the I
2
R loss dominates the
efficiency loss at medium to high load currents.
1. The V
IN
operating current comprises two components:
The DC supply current as given in the electrical charac-
teristics and the internal MOSFET gate charge currents.
The gate charge current results from switching the gate
capacitance of the internal power MOSFET switches.
Each time the gate is switched from high to low to
high again, a packet of charge, ∆Q, moves from V
IN
to
ground. The resulting ∆Q/dt is the current out of V
IN
that is typically larger than the DC bias current.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
and external inductor R
L
. When
switching, the average output current flowing through
the inductor is “chopped” between the high side PMOS
switch and the low side NMOS switch. Thus, the series
resistance looking back into the switch pin is a function
of the top and bottom switch R
DS(ON)
values and the
duty cycle (DC = V
OUT
/V
IN
) as follows:
R
SW
= (R
DS(ON)TOP
)DC + (R
DS(ON)BOT
) • (1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain the I
2
R losses, simply add
V
FB
SW
L1
L2
V
IN
RUN
R3
C
IN
C
OUT
V
OUT
5V
1A
C
SS
V
IN
R4
SS
V
PRG1
V
PRG2
FBO
LTC3630
(MASTER)
SW
V
FB
V
IN
RUN
SS
V
PRG1
V
PRG2
FBO
3630 F10
LTC3630
(SLAVE)
I
SET
I
SET
Figure 10. 5V, 1A Regulator