Datasheet

LTC3630A
16
3630afa
For more information www.linear.com/LTC3630A
applicaTions inForMaTion
Note that the soft-start capacitor may not be the limiting
factor in the output voltage ramp. The maximum output
current, which is equal to half the peak current, must
charge the output capacitor from 0V to its regulated value.
For small peak currents or large output capacitors, this
ramp time can be significant. Therefore, the output voltage
ramp time from 0V to the regulated V
OUT
value is limited
to a minimum of:
Ramp Time ≥
2 • C
OUT
I
PEAK
V
OUT
C
ISET
Selection
Once the peak current resistor, R
ISET
, and inductor are se-
lected to meet
the load current and frequency requirements,
an optional capacitor, C
ISET
, can be added in parallel with
R
ISET
. This will boost efficiency at mid-loads and reduce
the output voltage ripple dependency on load current at the
expense of slightly degraded load step transient response.
The peak inductor current is controlled by the voltage on
the I
SET
pin. Current out of the I
SET
pin is 5µA while the
LTC3630A is switching and is reduced to 1µA during sleep
mode. The I
SET
current will return to 5µA on the first cycle
after sleep mode. Placing a parallel RC from the I
SET
pin to
ground filters the I
SET
voltage as the LTC3630A enters and
exits sleep mode which in turn will affect the output volt-
age ripple
, efficiency and load step transient performance.
In
general, when R
ISET
is greater than 120k a C
ISET
ca-
pacitor in the 100pF to 200pF range will improve most
per
formance parameters. When R
ISET
is less than 100k,
the capacitance on the I
SET
pin should be minimized.
Higher Current Applications
For applications that require more
than 500
mA, the
LTC3630A provides a feedback comparator output pin
(FBO) for driving additional LTC3630As. When the FBO
pin of a “master” LTC3630A is connected to the V
FB
pin
of one or more “slave” LTC3630As, the master controls
the burst cycle of the slaves.
Figure 10 shows an example of a 5V, 1A regulator using
two LTC3630As. The master is configured for a 5V fixed
output with external soft-start and the V
IN
UVLO level is
set by the RUN pin. Since the slaves are directly controlled
V
FB
SW
L1
L2
V
IN
RUN
R3
C
IN
C
OUT
V
OUT
5V
1A
C
SS
V
IN
R4
SS
V
PRG1
V
PRG2
FBO
LTC3630A
(MASTER)
SW
V
FB
V
IN
RUN
SS
V
PRG1
V
PRG2
FBO
3630a F10
LTC3630A
(SLAVE)
I
SET
I
SET
Figure 10. 5V, 1A Regulator
by the master, the SS pin of the slave should have minimal
capacitance and the RUN pin of the slave should be floating.
Furthermore, slaves should be configured for a 1.8V fixed
output (V
PRG1
= V
PRG2
= SS) to set the V
FB
pin threshold at
1.8V. The inductors L1 and L2 do not necessarily have to
be the same, but should both meet the criteria described
above in the Inductor Selection section.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent
-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V
IN
operating current and I
2
R losses. The V
IN
operating current dominates the efficiency loss at very
low load currents whereas the I
2
R loss dominates the
efficiency loss at medium to high load currents.
1. The
V
IN
operating current comprises two components:
The DC supply current as given in the electrical charac-
teristics and
the internal MOSFET gate charge currents.